Datasheet > DS31256DK

DS31256DK

更新时间： 2024-11-10 23:48:51

品牌	Logo	应用领域
其他 - ETC		控制器
页数	文件大小	规格书
33页	354K
描述
256-Channel.High-Throughput HDLC Controller Demo Kit

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中文翻译

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数据手册

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DS31256DK 数据手册

DS31256DK Envoy

256-Channel, High-Throughput

HDLC Controller Demo Kit

www.maxim-ic.com

GENERAL DESCRIPTION

FEATURES

The DS31256 Envoy is a 256-channel HDLC

controller capable of handling up to 64 T1 or E1

data streams or two T3 data streams. Each of the

16 physical ports can handle one, two, or four T1

or E1 data streams. The Envoy is composed of

the following blocks: Layer 1, HDLC

processing, FIFO, DMA, PCI bus, and local bus.

Cꢀ256 Independent, Bidirectional HDLC

channels

CꢀUp to 132Mbps Full-Duplex Throughput

CꢀSupports Up to 64 T1 or E1 Data Streams

Cꢀ16 Physical Ports (16 Tx and 16 Rx) That

Can Be Independently Configured for

Channelized or Unchannelized Operation

CꢀThree Fast (52Mbps) Ports; Other Ports

Capable of Speeds Up to 10Mbps

(Unchannelized)

There are 16 HDLC engines (one for each port)

that are each capable of operating at speeds up to

8.192Mbps in channelized mode and up to

10Mbps in unchannelized mode. The Envoy also

has three fast HDLC engines that only reside on

Ports 0, 1, and 2. They can operate at speeds up

to 52Mbps.

CꢀChannelized Ports Can Each Handle One,

Two, or Four T1 or E1 Lines

CꢀPer-Channel DS0 Loopbacks in Both

Directions

CꢀOver-Subscription at the Port Level

CꢀTransparent Mode Supported

CꢀOn-Board Bit Error-Rate Tester (BERT)

with Automatic Error Insertion Capability

CꢀBERT function Can Be Assigned to Any

HDLC Channel or Any Port

APPLICATIONS

Channelized and Clear-Channel (Unchannelized)

T1/E1 and T3/E3

Routers with Multilink PPP Support

High-Density Frame-Relay Access

xDSL Access Multiplexers (DSLAMs)

Triple HSSI

CꢀLarge 16kB FIFO in Both Receive and

Transmit Directions

CꢀEfficient Scatter/Gather DMA Maximizes

Memory Efficiency

High-Density V.35

CꢀReceive Data Packets are Time-Stamped

CꢀTransmit Packet Priority Setting

CꢀV.54 Loopback Code Detector

CꢀLocal Bus Allows for PCI Bridging or Local

Access

SONET/SDH EOC/ECC Termination

ORDERING INFORMATION

PART

TEMP RANGE

PIN-PACKAGE

CꢀIntel or Motorola Bus Signals Supported

CꢀBackward Compatibility with DS3134

Cꢀ33MHz 32-Bit PCI (V2.1) Interface

Cꢀ3.3V Low-Power CMOS with 5V Tolerant

I/O

DS31256

0°C to +70°C

256 PBGA

CꢀJTAG Support IEEE 1149.1

Cꢀ256-Pin Plastic BGA (27mm x 27mm)

1 of 33

120302

12 3 4 5 6 7...33

中文翻译

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