Datasheet > DS31400GN2

DS31400GN2

更新时间： 2024-01-10 15:58:52

品牌	Logo	应用领域
美高森美 - MICROSEMI		ATM 异步传输模式
页数	文件大小	规格书
132页	1819K
描述
ATM/SONET/SDH IC,

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DS31400GN2 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.8
Base Number Matches：	1

DS31400GN2 数据手册

Data Sheet

April 2019

DS31400

8-Input, 14-Output, Dual DPLL Timing IC

with Sub-ps Output Jitter

General Description

Features

The DS31400 is a flexible, high-performance timing IC

for diverse frequency conversion and frequency

synthesis applications. On each of its eight input clocks

and 14 output clocks, the device can accept or generate

nearly any frequency between 2kHz and 750MHz. The

device offers two independent DPLLs to serve two

independent clock-generation paths.



Eight Input Clocks



Differential or CMOS/TTL Format

Any Frequency from 2kHz to 750MHz

Fractional Scaling for 64B/66B and FEC Scaling

(e.g., 64/66, 237/255, 238/255) or Any Other

Downscaling Requirement



Continuous Input Clock Quality Monitoring

Automatic or Manual Clock Selection

Three 2/4/8kHz Frame Sync Inputs

The input clocks are divided down, fractionally scaled as

needed, and continuously monitored for activity and

frequency accuracy. The best input clock is selected,

manually or automatically, as the reference clock for

each of the two flexible, high-performance digital PLLs.

Each DPLL locks to the selected reference and provides

programmable bandwidth, very high-resolution holdover

capability, and truly hitless switching between input

clocks. The digital PLLs are followed by a clock

synthesis subsystem that has seven fully programmable

digital frequency synthesis blocks, three high-speed

low-jitter APLLs, and 14 output clocks, each with its own

32-bit divider and phase adjustment. The APLLs provide

fractional scaling and output jitter less than 1ps RMS.



Two High-Performance DPLLs



Hitless Reference Switching on Loss of Input

Automatic or Manual Phase Build-Out

Holdover on Loss of All Inputs

Programmable Bandwidth, 0.5mHz to 400Hz



Seven Digital Frequency Synthesizers



Each Can Slave to Either DPLL

Produce Any 2kHz Multiple Up to 77.76MHz

Per-DFS Clock Phase Adjust

Three Output APLLs

For telecom systems, the device has all required

features and functions to serve as a central timing

function or as a line card timing IC. With a suitable

oscillator the device meets the requirements of Stratum

2, 3E, 3, 4E, and 4; G.812 Types I to IV; G.813; and

G.8262.



Output Frequencies to 750MHz

High Resolution Fractional Scaling for FEC and

64B/66B (e.g., 255/237, 255/238, 66/64) or Any

Other Scaling Requirement



Less than 1ps RMS Output Jitter

Simultaneously Produce Three Low-Jitter Rates

from the Same Reference (e.g., 622.08MHz for

SONET, 255/237 x 622.08MHz for OTU2, and

156.25MHz for 10GE)

Applications

Frequency Conversion Applications in a Wide Variety

of Equipment Types

Telecom Line Cards or Timing Cards with Any Mix of

SONET/SDH, Synchronous Ethernet, and/or

OTN Ports in WAN Equipment Including MSPPs,

Ethernet Switches, Routers, DSLAMs, and Base

Stations



14 Output Clocks in Seven Groups



Nearly Any Frequency from < 1Hz to 750MHz

Each Group Slaves to a DFS Clock, Any APLL

Clock, or Any Input Clock (Divided and Scaled)

Each Has a Differential Output (Three CML,

Four LVDS/LVPECL) and Separate CMOS/TTL

Output



Ordering Information

PART

TEMP RANGE

PIN-PACKAGE



32-Bit Frequency Divider Per Output

Two Sync Pulse Outputs: 8kHz and 2kHz

DS31400GN2

256 CSBGA

-40C to +85C

General Features

Suffix 2 denotes a lead(Pb)-free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.



Suitable Line Card IC or Timing Card IC for

Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU

Accepts and Produces Nearly Any Frequency

fom 1Hz to 750MHz

Internal Compensation for Local Oscillator

Frequency Error

Block Diagram appears on page 8.



SPI™ Processor Interface

1.8V Operation with 3.3V I/O (5V Tolerant)

17mm x 17mm CSGBA Package

12 3 4 5 6 7...132

中文翻译

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与DS31400GN2相关器件

型号	品牌	获取价格	描述	数据表
DS31404	MAXIM	获取价格	4-Input, 8-Output, Dual DPLL Timing IC with Sub-ps Output Jitter Differential
DS31404	MICROCHIP	获取价格	The DS31400 is a flexible, high-performance timing IC for diverse frequency conversion and
DS31404GN+	MAXIM	获取价格	4-Input, 8-Output, Dual DPLL Timing IC with Sub-ps Output Jitter Differential
DS31406	MAXIM	获取价格	2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter
DS31406	MICROCHIP	获取价格	The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and
DS31406GN+	MAXIM	获取价格	2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter
DS31407	MAXIM	获取价格	3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter Differential
DS31407	MICROCHIP	获取价格	The DS31407 is a flexible, high-performance timing IC for diverse frequency conversion and
DS31407GN+	MAXIM	获取价格	3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter Differential
DS31408	MAXIM	获取价格	8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock

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