Data Sheet
April 2019
DS31415
3-Input, 4-Output, Single DPLL Timing IC
with Sub-ps Output Jitter and 1588 Clock
General Description
Features
Three Input Clocks
The DS31415 is a flexible, high-performance timing IC
for diverse frequency conversion and frequency
synthesis applications. On each of its three input clocks
and four output clocks, the device can accept or
generate nearly any frequency between 2kHz and
750MHz.
Differential or CMOS/TTL Format
Any Frequency from 2kHz to 750MHz
Fractional Scaling for 64B/66B and FEC
Scaling (e.g. 64/66, 237/255, 238/255) or Any
Other Downscaling Requirement
Continuous Input Clock Quality Monitoring
Three 2/4/8kHz Frame Sync Inputs
The input clocks are divided down, fractionally scaled as
needed, and continuously monitored for activity and
frequency accuracy. The best input clock is selected,
manually or automatically, as the reference clock for the
rest of the device. A flexible, high-performance digital
PLL locks to the selected reference and provides
programmable bandwidth, very high resolution holdover
capability and truly hitless switching between input
clocks. The digital PLL is followed by a clock synthesis
subsystem which has two fully programmable digital
frequency synthesis blocks, a high-speed low-jitter
APLL, and four output clocks, each with its own 32-bit
divider and phase adjustment. The APLL provides
fractional scaling and output jitter less than 1ps rms. For
telecom systems, the DS31415 has all required features
and functions to serve as a central timing function or as
a line card timing IC.
High-Performance DPLL
Hitless Reference Switching on Loss of Input
Automatic or Manual Phase Build-Out
Holdover on Loss of All Inputs
Programmable Bandwidth, 0.5mHz to 400Hz
Two Digital Frequency Synthesizers
Produce Any 2kHz Multiple up to 77.76MHz
Per-DFS Phase Adjustment
High-Performance Output APLL
Output Frequencies to 750MHz
High Resolution Fractional Scaling for FEC
and 64B/66B (e.g. 255/237, 255/238, 66/64) or
Any Other Scaling Requirement
Less than 1ps rms Output Jitter
Four Output Clocks in Two Groups
Nearly Any Frequency from <1Hz to 750MHz
Each Group Slaves to a DFS Clock, Any APLL
Clock, or Any Input Clock (Divided and Scaled)
Each Has a Differential Output (3 CML, 4 LVDS/
LVPECL) AND Separate CMOS/TTL Output
32-Bit Frequency Divider Per Output
In addition the DS31415 has an embedded IEEE1588
clock that can be steered by system software to follow a
time master elsewhere in the system or elsewhere in
the network. This clock has all necessary features to be
the central time clock in a 1588 ordinary clock,
boundary clock or transparent clock.
Two Sync Pulse Outputs: 8kHz and 2kHz
IEEE1588 Clock Features
Applications
Frequency Conversion and IEEE1588 Time/Frequency
Applications in a Wide Variety of Equipment Types
Steerable by Software with 2-8ns Time
Resolution and 2-32ns Frequency Resolution
4ns Input Timestamp Accuracy and Output
Edge Placement Accuracy
Telecom Line Cards or Timing Cards with Any Mix of
SONET/SDH, Synchronous Ethernet and/or OTN
Ports in WAN Equipment Including MSPPs, Ethernet
Switches, Routers, DSLAMs, and Base Stations
Programmable Clock and Time-Alignment I/O to
Synchronize All 1588 Devices in Large Systems
Supports 1588 OC, BC and TC Architectures
General Features
Suitable Line Card IC or Timing Card IC for
Ordering Information
Stratum 2/3E/3/4E/4, SMC, SEC/EEC or SSU
Accepts and Produces Nearly Any Frequency
from 1Hz up to 750MHz
Internal Compensation for Local Oscillator
Frequency Error
PART
TEMP RANGE
PIN-PACKAGE
DS31415GN2
256 CSBGA (17mm)2
-40C to +85C
Suffix 2 denotes a lead-free/RoHS-compliant package.
SPI is a trademark of Motorola, Inc.
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
Block Diagram appears on page 9.
Register Map appears on page 54.
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