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DS31256+T PDF预览

DS31256+T

更新时间: 2024-01-04 14:59:55
品牌 Logo 应用领域
美信 - MAXIM 控制器
页数 文件大小 规格书
183页 1449K
描述
Telecom Circuit,

DS31256+T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:27 X 27 MM, 1.27 MM PITCH, PLASTIC, BGA-256针数:256
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.64
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:27 mm功能数量:1
端子数量:256最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:2.54 mm
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:27 mmBase Number Matches:1

DS31256+T 数据手册

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DEMO KIT AVAILABLE  
DS31256  
256-Channel, High-Throughput  
HDLC Controller  
www.maxim-ic.com  
GENERAL DESCRIPTION  
FEATURES  
The DS31256 Envoy is a 256-channel HDLC  
controller that can handle up to 60 T1 or 64 E1  
data streams or two T3 data streams. Each of the  
16 physical ports can handle one, two, or four  
T1 or E1 data streams. The DS31256 is  
composed of the following blocks: Layer 1,  
HDLC processing, FIFO, DMA, PCI bus, and  
local bus.  
Cꢀ256 Independent, Bidirectional HDLC  
Channels  
CꢀUp to 132Mbps Full-Duplex Throughput  
CꢀSupports Up to 60 T1 or 64 E1 Data Streams  
Cꢀ16 Physical Ports (16 Tx and 16 Rx) That  
Can Be Independently Configured for  
Channelized or Unchannelized Operation  
CꢀThree Fast (52Mbps) Ports; Other Ports  
Capable of Speeds Up to 10Mbps  
(Unchannelized)  
There are 16 HDLC engines (one for each port)  
that are each capable of operating at speeds up  
to 8.192Mbps in channelized mode and up to  
10Mbps in unchannelized mode. The DS31256  
Envoy also has three fast HDLC engines that  
only reside on Ports 0, 1, and 2. They are  
capable of operating at speeds up to 52Mbps.  
CꢀChannelized Ports Can Each Handle One,  
Two, or Four T1 or E1 Lines  
CꢀPer-Channel DS0 Loopbacks in Both  
Directions  
CꢀOver-Subscription at the Port Level  
CꢀTransparent Mode Supported  
CꢀOn-Board Bit Error-Rate Tester (BERT)  
with Automatic Error Insertion Capability  
CꢀBERT Function Can Be Assigned to Any  
HDLC Channel or Any Port  
APPLICATIONS  
Channelized and Clear-Channel  
(Unchannelized) T1/E1 and T3/E3  
Routers with Multilink PPP Support  
High-Density Frame-Relay Access  
xDSL Access Multiplexers (DSLAMs)  
Triple HSSI  
CꢀLarge 16kB FIFO in Both Receive and  
Transmit Directions  
CꢀEfficient Scatter/Gather DMA Maximizes  
Memory Efficiency  
CꢀReceive Data Packets are Time-Stamped  
CꢀTransmit Packet Priority Setting  
CꢀV.54 Loopback Code Detector  
CꢀLocal Bus Allows for PCI Bridging or Local  
Access  
High-Density V.35  
SONET/SDH EOC/ECC Termination  
ORDERING INFORMATION  
PART  
TEMP RANGE  
PIN-PACKAGE  
CꢀIntel or Motorola Bus Signals Supported  
CꢀBackward Compatibility with DS3134  
Cꢀ33MHz 32-Bit PCI (V2.1) Interface  
Cꢀ3.3V Low-Power CMOS with 5V Tolerant  
I/O  
DS31256  
0°C to +70°C  
256 PBGA  
CꢀJTAG Support IEEE 1149.1  
Cꢀ256-Pin Plastic BGA (27mm x 27mm)  
Features continued on page 6.  
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device  
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.  
1 of 183  
REV: 031405  

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