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DS26504LN PDF预览

DS26504LN

更新时间: 2024-11-08 22:36:31
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
128页 1175K
描述
T1/E1/J1/64KCC BITS Element

DS26504LN 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:10 X 10 MM, 1.40 MM HEIGHT, LQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
运营商类型:CEPT PCM-30/E-1运营商类型(2):T-1(DS1)
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm湿度敏感等级:3
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):245
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Other Telecom ICs
最大压摆率:0.15 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:FRAMER
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

DS26504LN 数据手册

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DS26504  
T1/E1/J1/64KCC BITS Element  
www.maxim-ic.com  
Cꢀ Transmit and Receive T1 BOC SSM Messages  
with Receive Message Change of State and  
Validation Indication  
GENERAL DESCRIPTION  
The DS26504 is a building-integrated timing-supply  
(BITS) clock-recovery element. It also functions as a  
basic T1/E1 transceiver. The receiver portion can  
recover a clock from T1, E1, 64kHz composite clock  
(64KCC), and 6312kHz synchronization timing  
interfaces. In T1 and E1 modes, the Synchronization  
Status Message (SSM) can also be recovered. The  
transmit portion can directly interface to T1, E1, or  
64KCC synchronization interfaces as well as source  
the SSM in T1 and E1 modes. The DS26504 can  
translate between any of the supported inbound  
synchronization clock rates to any supported  
outbound rate. The DS26504 can also accept an 8kHz  
as well as a 19.44MHz reference clock. A separate  
output is provided to source a 6312kHz clock. The  
device is controlled through a parallel, serial, or  
hardware controller port.  
Cꢀ Transmit and Receive E1 Sa(n) Bit SSM  
Messages with Receive Message Change of State  
Indication  
Cꢀ Crystal-Less Jitter Attenuator with Bypass Mode  
for T1 and E1 Operation  
Cꢀ Fully Independent Transmit and Receive  
Functionality  
Cꢀ Internal Software-Selectable Receive and  
Transmit Side Termination for  
75/100/110/120/133Ω  
Cꢀ Monitor Mode for Bridging Applications  
Cꢀ Accepts 16.384MHz, 12.8MHz, 8.192MHz,  
4.096MHz, 2.048MHz, or 1.544MHz Master  
Clock  
Cꢀ 64kHz, 8kHz, and 400Hz Outputs in Composite  
Clock Mode  
Cꢀ 8-Bit Parallel Control Port, Multiplexed or  
Nonmultiplexed, Intel or Motorola  
Cꢀ Serial (SPI) Control Port and Hardware Control  
Mode  
APPLICATIONS  
BITS Timing  
Rate Conversion  
Cꢀ Provides LOS, AIS, and LOF Indications through  
Hardware Output Pins  
FEATURES  
Cꢀ Fast Transmitter Output Disable through Device  
Pin for Protection Switching  
Cꢀ Accepts 8kHz and 19.44MHz References in  
Addition to T1, E1, and 64kHz Composite Clock  
Cꢀ GR378 Composite Clock Compliant  
Cꢀ G.703 2048kHz Synchronization Interface  
Compliant  
Cꢀ IEEE 1149.1 JTAG Boundary Scan  
Cꢀ 3.3V Supply with 5V Tolerant Inputs and  
Outputs  
Cꢀ Pin and Software Compatible with the DS26502  
and DS26503  
Cꢀ G.703 64kHz Option A & B Centralized Clock  
Synchronization Interface Compliant  
Cꢀ G.703 64kHz Japanese Composite Clock  
Synchronization Interface Compliant  
Cꢀ G.703 6312kHz Japanese Synchronization  
Interface Compliant  
ORDERING INFORMATION  
PART  
TEMP RANGE PIN-PACKAGE  
Cꢀ Interfaces to Standard T1/J1 (1.544MHz) and E1  
(2.048MHz)  
DS26504L  
0°C to +70°C  
64 LQFP  
Cꢀ Interface to CMI-Coded T1/J1 and E1  
Cꢀ T1/E1 Transmit Payload Clock Output  
Cꢀ Short- and Long-Haul Line Interface  
DS26504LN -40°C to +85°C 64 LQFP  
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device  
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.  
1 of 128  
REV: 070105  

DS26504LN 替代型号

型号 品牌 替代类型 描述 数据表
DS26504L+ MAXIM

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