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DS26504LN+T&R PDF预览

DS26504LN+T&R

更新时间: 2024-11-23 15:31:07
品牌 Logo 应用领域
美信 - MAXIM 电信电信集成电路
页数 文件大小 规格书
129页 1167K
描述
Framer,

DS26504LN+T&R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.75峰值回流温度(摄氏度):NOT SPECIFIED
电信集成电路类型:FRAMER处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

DS26504LN+T&R 数据手册

 浏览型号DS26504LN+T&R的Datasheet PDF文件第2页浏览型号DS26504LN+T&R的Datasheet PDF文件第3页浏览型号DS26504LN+T&R的Datasheet PDF文件第4页浏览型号DS26504LN+T&R的Datasheet PDF文件第5页浏览型号DS26504LN+T&R的Datasheet PDF文件第6页浏览型号DS26504LN+T&R的Datasheet PDF文件第7页 
DESIGN KIT AVAILABLE  
DS26504  
T1/E1/J1/64KCC BITS Element  
www.maxim-ic.com  
Transmit and Receive T1 BOC SSM Messages  
with Receive Message Change of State and  
Validation Indication  
Transmit and Receive E1 Sa(n) Bit SSM  
Messages with Receive Message Change of State  
Indication  
Crystal-Less Jitter Attenuator with Bypass Mode  
for T1 and E1 Operation  
Fully Independent Transmit and Receive  
Functionality  
Internal Software-Selectable Receive and  
Transmit Side Termination for  
75/100/110/120/133Ω  
Monitor Mode for Bridging Applications  
Accepts 16.384MHz, 12.8MHz, 8.192MHz,  
4.096MHz, 2.048MHz, or 1.544MHz Master  
Clock  
64kHz, 8kHz, and 400Hz Outputs in Composite  
Clock Mode  
8-Bit Parallel Control Port, Multiplexed or  
Nonmultiplexed, Intel or Motorola  
Serial (SPI) Control Port and Hardware Control  
Mode  
GENERAL DESCRIPTION  
The DS26504 is a building-integrated timing-supply  
(BITS) clock-recovery element. It also functions as a  
basic T1/E1 transceiver. The receiver portion can  
recover a clock from T1, E1, 64kHz composite clock  
(64KCC), and 6312kHz synchronization timing  
interfaces. In T1 and E1 modes, the Synchronization  
Status Message (SSM) can also be recovered. The  
transmit portion can directly interface to T1, E1, or  
64KCC synchronization interfaces as well as source  
the SSM in T1 and E1 modes. The DS26504 can  
translate between any of the supported inbound  
synchronization clock rates to any supported  
outbound rate. The DS26504 can also accept an 8kHz  
as well as a 19.44MHz reference clock. A separate  
output is provided to source a 6312kHz clock. The  
device is controlled through a parallel, serial, or  
hardware controller port.  
APPLICATIONS  
BITS Timing  
Rate Conversion  
Provides LOS, AIS, and LOF Indications through  
Hardware Output Pins  
Fast Transmitter Output Disable through Device  
Pin for Protection Switching  
IEEE 1149.1 JTAG Boundary Scan  
3.3V Supply with 5V Tolerant Inputs and  
Outputs  
Pin and Software Compatible with the DS26502  
and DS26503  
FEATURES  
Accepts 8kHz and 19.44MHz References in  
Addition to T1, E1, and 64kHz Composite Clock  
GR378 Composite Clock Compliant  
G.703 2048kHz Synchronization Interface  
Compliant  
G.703 64kHz Option A & B Centralized Clock  
Synchronization Interface Compliant  
G.703 64kHz Japanese Composite Clock  
Synchronization Interface Compliant  
G.703 6312kHz Japanese Synchronization  
Interface Compliant  
ORDERING INFORMATION  
PART  
TEMP RANGE PIN-PACKAGE  
0°C to +70°C 64 LQFP  
Interfaces to Standard T1/J1 (1.544MHz) and E1  
(2.048MHz)  
DS26504L  
Interface to CMI-Coded T1/J1 and E1  
T1/E1 Transmit Payload Clock Output  
Short- and Long-Haul Line Interface  
DS26504LN -40°C to +85°C 64 LQFP  
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device  
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.  
1 of 129  
REV: 072308  

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