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DS26101N

更新时间： 2024-11-23 20:51:47
品牌 Logo 应用领域
美信 - MAXIM ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
62页 679K
描述
ATM Network Interface, 1-Func, PBGA256, 17 X 17 MM, CSBGA-256

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中文翻译

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DS26101N 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：LBGA,
针数：256Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.9
JESD-30 代码：S-PBGA-B256JESD-609代码：e0
长度：17 mm功能数量：1
端子数量：256最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：245
认证状态：Not Qualified座面最大高度：1.5 mm
标称供电电压：3.3 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH NETWORK INTERFACE温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：17 mm
Base Number Matches：1

DS26101N 数据手册

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DS26101  
8-Port Transmission  
Convergence Device  
www.maxim-ic.com  
GENERAL DESCRIPTION  
FEATURES  
On the transmit side, the DS26101 receives ATM cells  
from an ATM device through a UTOPIA II interface,  
provides cell buffering (up to 4 cells), HEC generation  
and insertion, cell scrambling, and converts the data  
to a serial stream appropriate for interfacing to a  
T1/E1 framer or transceiver. On the receive side, the  
DS26101 receives a TDM stream from a T1/E1 framer  
or transceiver; searches for the cell alignment; verifies  
the HEC; provides cell filtering, descrambling, and cell  
buffering; and passes the cells to an ATM device  
through the UTOPIA II interface. Other low-level traffic  
management functions are selectable for the transmit  
and receive paths. The DS26101 can also be used in  
fractional T1/E1 applications.  
Cꢀ Supports 8 T1/E1 TDM Ports  
Cꢀ Supports Fractional T1/E1  
Cꢀ Compliant to ATM Forum Specifications for ATM  
Over T1 and E1  
Cꢀ Standard UTOPIA II Interface to the ATM Layer  
Cꢀ Configurable UTOPIA Address Range  
Cꢀ Configurable Tx FIFO Depth to 2, 3, or 4 Cells  
Cꢀ Optional Payload Scrambling in Transmit  
Direction and Descrambling in Receive Direction  
per ITU I.432  
Cꢀ Optional HEC Insertion in Transmit Direction with  
Programmable COSET Polynomial Addition  
Cꢀ HEC-Based Cell Delineation  
Cꢀ Single-Bit HEC Error Correction in the Receive  
Direction  
The DS26101 maps ATM cells to T1/E1 TDM frames  
as specified in ATM Forum Specifications af-phy-  
0016.000 and af-phy-0064.000. In the receive  
direction, the cell delineation mechanism used for  
finding ATM cell boundary within T1/E1 frame is  
performed as per ITU I.432. The DS26101 provides a  
mapping solution for up to 8 T1/E1 TDM ports. The  
terms physical layer (PHY) and line side are used  
synonymously in this document and refer to the  
device interfacing with the line side of the DS26101.  
The terms ATM layer and system side are used  
synonymously and refer to the DS26101’s UTOPIA II  
interface.  
Cꢀ Receive HEC-Errored Cell Filtering  
Cꢀ Receive Idle/Unassigned Cell Filtering  
Cꢀ User-Definable Cell Filtering  
Cꢀ 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor  
Interface  
Cꢀ Internal Clock Generator Eliminates External  
High-Speed Clocks  
Cꢀ Internal One-Second Timer  
Cꢀ Detects/Reports Up to Eight External Status  
Signals with Interrupt Support  
Cꢀ IEEE 1149.1 JTAG Boundary Scan Support  
Cꢀ 17mm x 17mm, 256-pin CSBGA  
APPLICATIONS  
FUNCTIONAL DIAGRAM  
DSLAMS  
ATM Over T1/E1  
Routers  
IMA  
Dallas  
ORDERING INFORMATION  
Semiconductor  
8 TDM  
DS26101  
UTOPIA II  
PART  
TEMP RANGE  
PIN-PACKAGE  
PORTS  
DS26101  
-40°C to +85°C  
256 CSBGA  
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device  
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.  
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REV: 032805  
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