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DS26102 PDF预览

DS26102

更新时间： 2024-11-26 04:15:11
品牌 Logo 应用领域
美信 - MAXIM ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
64页 597K
描述
16-Port TDM-to-ATM PHY

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中文翻译

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DS26102 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：17 X 17 MM, CSBGA-256
针数：256Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.78
应用程序：ATMJESD-30 代码：S-PBGA-B256
JESD-609代码：e0长度：17 mm
功能数量：1端子数量：256
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：245认证状态：Not Qualified
座面最大高度：1.5 mm标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH NETWORK INTERFACE
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：17 mmBase Number Matches：1

DS26102 数据手册

 浏览型号DS26102的Datasheet PDF文件第2页浏览型号DS26102的Datasheet PDF文件第3页浏览型号DS26102的Datasheet PDF文件第4页浏览型号DS26102的Datasheet PDF文件第5页浏览型号DS26102的Datasheet PDF文件第6页浏览型号DS26102的Datasheet PDF文件第7页 
DS26102  
16-Port TDM-to-ATM PHY  
www.maxim-ic.com  
GENERAL DESCRIPTION  
FEATURES  
On the transmit side, the DS26102 receives ATM cells  
from an ATM device through a UTOPIA II interface,  
provides cell buffering (up to 4 cells), HEC generation  
and insertion, cell scrambling, and converts the data  
to a serial stream appropriate for interfacing to a  
T1/E1 framer or transceiver. On the receive side, the  
DS26102 receives a TDM stream from a T1/E1 framer  
or transceiver; searches for the cell alignment; verifies  
the HEC; provides cell filtering, descrambling, and cell  
buffering; and passes the cells to an ATM device  
through the UTOPIA II interface. Other low-level traffic  
management functions are selectable for the transmit  
and receive paths. The DS26102 can also be used in  
fractional T1/E1 applications.  
Cꢀ Supports 16 T1/E1 TDM Ports  
Cꢀ Supports Fractional T1/E1  
Cꢀ Compliant to ATM Forum Specifications for ATM  
Over T1 and E1  
Cꢀ Standard UTOPIA II Interface to the ATM Layer  
Cꢀ Configurable UTOPIA Address Range  
Cꢀ Configurable Tx FIFO Depth to 2, 3, or 4 Cells  
Cꢀ Optional Payload Scrambling in Transmit  
Direction and Descrambling in Receive Direction  
per ITU I.432  
Cꢀ Optional HEC Insertion in Transmit Direction with  
Programmable COSET Polynomial Addition  
Cꢀ HEC-Based Cell Delineation  
Cꢀ Single-Bit HEC Error Correction in the Receive  
Direction  
The DS26102 maps ATM cells to T1/E1 TDM frames  
as per the ATM Forum Specifications af-phy-0016.000  
and af-phy-0064.000. In the receive direction, the cell  
delineation mechanism used for finding ATM cell  
boundary within T1/E1 frame is performed as per ITU  
I.432. The DS26102 provides a mapping solution for  
up to 16 T1/E1 TDM ports. The terms physical layer  
(PHY) and line side are used synonymously in this  
document and refer to the device interfacing with the  
line side of the DS26102. The terms ATM layer and  
system side are used synonymously and refer to the  
DS26102’s UTOPIA II interface.  
Cꢀ Receive HEC-Errored Cell Filtering  
Cꢀ Receive Idle/Unassigned Cell Filtering  
Cꢀ User-Definable Cell Filtering  
Cꢀ 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor  
Interface  
Cꢀ Internal Clock Generator Eliminates External  
High-Speed Clocks  
Cꢀ Internal One-Second Timer  
Cꢀ Detects/Reports Up to Eight External Status  
Signals with Interrupt Support  
Cꢀ IEEE 1149.1 JTAG Boundary Scan Support  
Cꢀ 17mm x 17mm, 256-Pin CSBGA  
Features continued on page 5.  
FUNCTIONAL DIAGRAM  
APPLICATIONS  
DSLAMS  
ATM Over T1/E1  
Routers  
IMA  
16 TDM  
DS26102 UTOPIA II  
PORTS  
ORDERING INFORMATION  
PART  
TEMP RANGE  
PIN-PACKAGE  
DS26102  
-40°C to +85°C  
256 CSBGA  
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device  
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.  
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中文翻译

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