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DP8473V

更新时间： 2024-11-29 23:16:31
品牌 Logo 应用领域
美国国家半导体 - NSC 存储微控制器和处理器次级存储控制器外围集成电路数据传输PC
页数 文件大小 规格书
28页 358K
描述
DP8473 Floppy Disk Controller PLUS-2

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中文翻译

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DP8473V 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCJ, LDCC52,.8SQReach Compliance Code：unknown
风险等级：5.8Is Samacsys：N
最大数据传输速率：0.125 MBps外部数据总线宽度：8
主机接口标准：PC-AT; PC-XT; PS/2JESD-30 代码：S-PQCC-J52
JESD-609代码：e0端子数量：52
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC52,.8SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
子类别：Secondary Storage Controllers最大压摆率：20 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIEDuPs/uCs/外围集成电路类型：SECONDARY STORAGE CONTROLLER, FLOPPY DISK DRIVE
Base Number Matches：1

DP8473V 数据手册

 浏览型号DP8473V的Datasheet PDF文件第2页浏览型号DP8473V的Datasheet PDF文件第3页浏览型号DP8473V的Datasheet PDF文件第4页浏览型号DP8473V的Datasheet PDF文件第5页浏览型号DP8473V的Datasheet PDF文件第6页浏览型号DP8473V的Datasheet PDF文件第7页 
July 1990  
DP8473 Floppy Disk Controller PLUS-2TM  
General Description  
Features  
Y
Fully mPD765A and IBM-BIOS compatible  
This controller is a full featured floppy disk controller that is  
software compatible with the mPD765A, but also includes  
many additional hardware and software enhancements.  
These enhancements include additional logic specifically re-  
quired for an IBM PC, PC-XT , PC-AT , or PS/2 design.  
Y
Integrates all PCXT , PCAT , and most PS/2 Logic  
É
Ð On chip 24 MHz Crystal Oscillator  
Ð DMA enable logic  
É
É
Ð IBM compatible address decode of A0–A2  
Ð 12 mA mP bus interface buffers  
Ð 48 mA floppy drive interface buffers  
Ð Data rate and drive control registers  
Precision analog data separator  
É
É
É
É
This controller incorporates a precision analog data separa-  
tor, that includes a self trimming delay line and VCO. Up to  
three external filters are switched automatically depending  
on the data rate selected. This provides optimal perform-  
ance at the standard PC data rates of 250/300 kb/s, and  
500 kb/s. It also enables optimum performance at 1 Mb/s  
(MFM). These features combine to provide the lowest possi-  
ble PLL bandwidth, with the greatest lock range, and hence  
the widest window margin.  
Y
Ð Self-calibrating PLL and delay line  
Ð Automatically chooses one of three filters  
Ð Intelligent read algorithm  
Y
Y
Two pin programmable precompensation modes  
Other enhancements  
Ð up to 1 Mb/s data rate  
This controller includes write precompensation circuitry. A  
shift register is used to provide a fixed 125 ns early-late  
precompensation for all tracks at 500k/300k/250 kb/s (83  
ns for 1 MB/s), or a precompensation value that scales with  
(Continued)  
Ð Implied seek up to 4000 tracks  
Ð IBM or ISO formatting  
Y
Low power CMOS, with power down mode  
Connection Diagrams  
Plastic Leaded Chip Carrier  
Dual-In-Line Package  
TL/F/9384–1  
Top View  
Order Number DP8473V  
See NS Package Number V52A  
TL/F/9384–2  
Top View  
Order Number DP8473N  
See NS Package Number N48A  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
PLUS-2TM is a trademark of National Semiconductor Corporation.  
IBMÉ, PCXTÉ, PCATÉ and PS/2É are registered trademarks of International Business Machines Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9384  
RRD-B30M105/Printed in U. S. A.  
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