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DP8481J PDF预览

DP8481J

更新时间: 2024-11-29 23:16:31
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器电平转换器
页数 文件大小 规格书
6页 113K
描述
TTL to 10k ECL Level Translator with Latch

DP8481J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.91最大延迟:
输入特性:STANDARD接口集成电路类型:TTL TO ECL TRANSLATOR
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.43 mm位数:5
功能数量:1端子数量:16
最高工作温度:75 °C最低工作温度:
输出特性:OPEN-EMITTER输出锁存器或寄存器:LATCH
输出极性:INVERTED封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5,-5.2 V
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Level Translators表面贴装:NO
技术:BIPOLAR温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

DP8481J 数据手册

 浏览型号DP8481J的Datasheet PDF文件第2页浏览型号DP8481J的Datasheet PDF文件第3页浏览型号DP8481J的Datasheet PDF文件第4页浏览型号DP8481J的Datasheet PDF文件第5页浏览型号DP8481J的Datasheet PDF文件第6页 
June 1986  
DP8481 TTL to 10k ECL Level Translator with Latch  
General Description  
Features  
Y
16-pin flat-pack or DIP  
This circuit translates TTL input levels to ECL output levels  
and provides a fall-through latch. The outputs are gated with  
CS providing for wire ORing of outputs. The strobe and chip  
select inputs operate at ECL levels.  
Y
ECL control inputs  
Y
CS provided for wire ORing of output bus  
Y
10k ECL I/O compatible  
Y
3.0 ns typical propagation delay  
Logic and Connection Diagram  
Truth Table  
D
Q
STR  
CS  
Dual-In-Line Package  
H
L
L
H
Q
L
L
L
H
H
H
L
X
X
H
X
e
H
high level (most positive)  
low level (most negative)  
don’t care  
e
e
L
X
Order Number  
DP8481F, DP8481J or DP8481N  
See NS Package  
F16B, J16A or N16A  
TL/F/5862–1  
Top View  
C
1995 National Semiconductor Corporation  
TL/F/5862  
RRD-B30M115/Printed in U. S. A.  

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