DP8483N

更新时间： 2024-09-29 23:16:31

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器电平转换器接口集成电路
页数	文件大小	规格书
6页	120K
描述
TTL to 100k ECL Level Translator with Latch

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DP8483N 数据手册

April 1990

DP8483 TTL to 100k ECL Level Translator with Latch

General Description

Features

16-pin DIP or S.O.

This circuit translates TTL input levels to ECL output levels

and provides a fall-through latch. The outputs are gated with

CS providing for wire ORing of outputs. The strobe and chip

select inputs operate at ECL levels.

ECL control inputs

CS provided for wire ORing of output bus

100k ECL I/O compatible

3.0 ns typical propagation delay

Logic and Connection Diagram

Truth Table

Dual-In-Line Package

STR

high level (most positive)

low level (most negative)

don’t care

Order Number DP8483J,

DP8483M or DP8483N

See NS Package Number J16A, M16B or N16A

TL/F/5864–1

Top View

1995 National Semiconductor Corporation

TL/F/5864

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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