DP84902

更新时间： 2024-11-30 22:23:55

品牌	Logo	应用领域
美国国家半导体 - NSC		解码器编码器
页数	文件大小	规格书
16页	211K
描述
1,7 Encoder/Decoder Circuit

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DP84902 数据手册

June 1994

DP84902

1,7 Encoder/Decoder Circuit

General Description

The DP84902 is designed to perform the encoding and de-

coding for disk memory systems. It is designed to interface

directly with Integrated Read Channel Products (such as

National Semiconductor’s DP84910) and with Disk Data

Controller Products with a 2-bit NRZ interface (such as Na-

tional Semiconductor’s Advanced Disk Controllers). This

Encoder/Decoder (ENDEC) circuit employs a 2/3 (1,7) Run

Length Limited (RLL) code type and supports the hard sec-

tored format.

The DP84902 is available in 20-pin SO and 20-pin SSO

packages.

Features

Operates at 2-bit Non-Return to Zero (NRZ) Data Rates

up to 50 Mbits/second

Single 5V Power Supply Operation

Low Power Dissipation when TTL compatible code out-

put is selected. 150 mW at 50 Mbits/second NRZ Rate

TTL Compatible Inputs and Outputs

ECL Compatible Code Outputs (patented) are control

The DP84902 has the option of selecting either TTL or ECL

compatible code output to interface with preamplifiers com-

monly used in high data rate applications. This is accomm-

plished by the setting of a bit in the control register.

Two-bit NRZ Interface

The ENDEC also includes write data precompensation con-

trol circuitry which detects the need for write precompensa-

tion. This circuitry issues early and late output signals nec-

essary for precompensation. The precompensation informa-

tion is generated against a 2T pattern. The precompensa-

tion circuitry can be bypassed by the setting of a bit in the

control register.

Supports Write Data Precompensation with Early and

Late output signals

Selectable use of either an Internal or External Write

Clock

Power Down Mode Included

DC-Erasure is available to support Analog Flaw Map-

ping Testing

A control reigster is included to configure the ENDEC and to

select device operation options such as output code inver-

sion, differential code output, bypassing of the encoder, and

the use of an internal write clock.

Bypass Mode available which permits Un-Encoded Test

Patterns to be issued at the CODEOUT Pin

Block Diagram

TL/F/11963–1

FIGURE 1. DP84902 ENDEC Block Diagram

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

IBMÉ is a registered trademark of International Business Machines Corporation.

1995 National Semiconductor Corporation

TL/F/11963

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7...16

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与DP84902相关器件

型号	品牌	获取价格	描述	数据表
DP84902M	NSC	获取价格	1,7 Encoder/Decoder Circuit
DP84902MS	NSC	获取价格	1,7 Encoder/Decoder Circuit
DP84902MSX	TI	获取价格	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20, SHRINK, SOP-20
DP84902MX	TI	获取价格	SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20, SOP-20
DP8490N	ETC	获取价格	Controller Miscellaneous - Datasheet Reference
DP8490V	NSC	获取价格	IC SCSI BUS CONTROLLER, PQCC44, PLASTIC, CC-44, Bus Controller
DP84910	NSC	获取价格	Integrated Read Channel
DP84910-36	NSC	获取价格
DP84910-50	NSC	获取价格
DP84910VHG	NSC	获取价格	IC,DISK DATA SEP/SYNCHRONIZER,QFP,80PIN,PLASTIC

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