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DP84T22-25 PDF预览

DP84T22-25

更新时间： 2023-12-18 00:00:00
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动器微控制器和处理器内存控制器
页数 文件大小 规格书
60页 821K
描述
microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

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中文翻译

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DP84T22-25 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：,针数：84
Reach Compliance Code：unknown风险等级：5.84
技术：CMOSuPs/uCs/外围集成电路类型：MEMORY CONTROLLER, DRAM
Base Number Matches：1

DP84T22-25 数据手册

 浏览型号DP84T22-25的Datasheet PDF文件第2页浏览型号DP84T22-25的Datasheet PDF文件第3页浏览型号DP84T22-25的Datasheet PDF文件第4页浏览型号DP84T22-25的Datasheet PDF文件第5页浏览型号DP84T22-25的Datasheet PDF文件第6页浏览型号DP84T22-25的Datasheet PDF文件第7页 
May 1992  
DP8420V/21V/22V-33, DP84T22-25 microCMOS  
Programmable 256k/1M/4M Dynamic RAM  
Controller/Drivers  
General Description  
Features  
Y
On chip high precision delay line to guarantee critical  
DRAM access timing parameters  
The DP8420V/21V/22V-33, DP84T22-25 dynamic RAM  
controllers provide a low cost, single chip interface between  
dynamic RAM and all 8-, 16- and 32-bit systems. The  
DP8420V/21V/22V-33, DP84T22-25 generate all the re-  
quired access control signal timing for DRAMs. An on-chip  
refresh request clock is used to automatically refresh the  
DRAM array. Refreshes and accesses are arbitrated on  
chip. If necessary, a WAIT or DTACK output inserts wait  
states into system access cycles, including burst mode ac-  
cesses. RAS low time during refreshes and RAS precharge  
time after refreshes and back to back accesses are guaran-  
teed through the insertion of wait states. Separate on-chip  
precharge counters for each RAS output can be used for  
memory interleaving to avoid delayed back to back access-  
es because of precharge. An additional feature of the  
DP8422V, DP84T22 is two access ports to simplify dual ac-  
cessing. Arbitration among these ports and refresh is done  
on chip. To make board level circuit testing easier the  
Y
Y
microCMOS process for low power  
High capacitance drivers for RAS, CAS, WE and DRAM  
address on chip  
Y
On chip support for nibble, page and static column  
DRAMs  
Y
Y
TRI-STATE outputs (DP84T22 only)  
Byte enable signals on chip allow byte writing in a word  
size up to 32 bits with no external logic  
Selection of controller speeds: 25 MHz and 33 MHz  
On board Port A/Port B (DP8422V, DP84T22 only)/re-  
fresh arbitration logic  
Y
Y
Y
Y
Direct interface to all major microprocessors (applica-  
tion notes available)  
4 RAS and 4 CAS drivers (the RAS and CAS configura-  
tion is programmable)  
DP84T22 incorporates TRI-STATE output buffers.  
É
Largest  
DRAM  
Possible  
Direct Drive  
Memory  
Capacity  
Access  
Ports  
Available  
Ý
Ý
of Pins  
(PLCC)  
of Address  
Outputs  
Control  
DP8420V  
DP8421V  
DP8422V  
DP84T22  
68  
68  
84  
84  
9
256 kbit  
1 Mbit  
4 Mbit  
4 Mbit  
4 Mbytes  
16 Mbytes  
64 Mbytes  
64 Mbytes  
Single Access Port  
10  
11  
11  
Single Access Port  
Dual Access Ports (A and B)  
Dual Access and TRI-STATE  
Block Diagram  
DP8420V/21V/22V, DP74T22 DRAM Controller  
TL/F/11109–1  
FIGURE 1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
Staggered RefreshTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/11109  
RRD-B30M105/Printed in U. S. A.  
1234567...60

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