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DP8570AVX/NOPB

更新时间： 2024-02-24 05:17:08
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟双倍数据速率外围集成电路
页数 文件大小 规格书
26页 378K
描述
IC 2 TIMER(S), REAL TIME CLOCK, PQCC28, PLASTIC, LCC-28, Timer or RTC

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DP8570AVX/NOPB 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：PLASTIC, LCC-28Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.16其他特性：4 PROGRAMMABLE MODES FOR TIMER; 4 SELECTABLE OSCILLATOR FREQUENCIES
外部数据总线宽度：8信息访问方法：PARALLEL, DIRECT ADDRESS
中断能力：YJESD-30 代码：S-PQCC-J28
JESD-609代码：e3长度：11.43 mm
湿度敏感等级：2A位数：16
端子数量：28计时器数量：2
片上数据RAM宽度：8最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：2.4576 MHz
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：245
电源：3/5 V认证状态：Not Qualified
RAM（字数）：44座面最大高度：4.57 mm
子类别：Timer or RTC最大压摆率：20 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
最短时间：1/100 SECOND处于峰值回流温度下的最长时间：30
易失性：YES宽度：11.43 mm
uPs/uCs/外围集成电路类型：TIMER, REAL TIME CLOCKBase Number Matches：1

DP8570AVX/NOPB 数据手册

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May 1993  
DP8570A Timer Clock Peripheral (TCP)  
General Description  
The DP8570A is intended for use in microprocessor based  
systems where information is required for multi-tasking, data  
logging or general time of day/date information. This device  
is implemented in low voltage silicon gate microCMOS tech-  
nology to provide low standby power in battery back-up en-  
vironments. The circuit’s architecture is such that it looks  
like a contiguous block of memory or I/O ports. The address  
space is organized as 2 software selectable pages of 32  
bytes. This includes the Control Registers, the Clock Coun-  
ters, the Alarm Compare RAM, the Timers and their data  
RAM, and the Time Save RAM. Any of the RAM locations  
that are not being used for their intended purpose may be  
used as general purpose CMOS RAM.  
interrupt, and lock out the mp interface. The time power fails  
l
Additionally, two supply pins are provided. When V  
may be logged into RAM automatically when V  
BB  
V
.
CC  
l
, internal circuitry will automatically switch from the main  
BB  
V
CC  
supply to the battery supply. Status bits are provided to indi-  
cate initial application of battery power, system power, and  
low battery detect.  
(Continued)  
Features  
Y
Full function real time clock/calendar  
Ð 12/24 hour mode timekeeping  
Ð Day of week and day of years counters  
Ð Four selectable oscillator frequencies  
Ð Parallel Resonant Oscillator  
Time and date are maintained from 1/100 of a second to  
year and leap year in a BCD format, 12 or 24 hour modes.  
Day of week, day of month and day of year counters are  
provided. Time is controlled by an on-chip crystal oscillator  
requiring only the addition of the crystal and two capacitors.  
The choice of crystal frequency is program selectable.  
Y
Two 16-bit timers  
Ð 10 MHz external clock frequency  
Ð Programmable multi-function output  
Ð Flexible re-trigger facilities  
Y
Power fail features  
Two independent multifunction 10 MHz 16-bit timers are  
provided. These timers operate in four modes. Each has its  
own prescaler and can select any of 8 possible clock inputs.  
Thus, by programming the input clocks and the timer coun-  
ter values a very wide range of timing durations can be  
achieved. The range is from about 400 ns (4.915 MHz oscil-  
lator) to 65,535 seconds (18 hrs., 12 min.).  
Ð Internal power supply switch to external battery  
Ð Power Supply Bus glitch protection  
Ð Automatic log of time into RAM at power failure  
On-chip interrupt structure  
Ð Periodic, alarm, timer and power fail interrupts  
Up to 44 bytes of CMOS RAM  
Y
Y
Y
INTR/MFO/T1 pins programmable High/Low and push-  
pull or open drain  
Power failure logic and control functions have been integrat-  
ed on chip. This logic is used by the TCP to issue a power fail  
Block Diagram  
TL/F/8638–1  
FIGURE 1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/8638  
RRD-B30M75/Printed in U. S. A.  
1234567...26

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