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DP8573AV PDF预览

DP8573AV

更新时间: 2024-01-08 07:00:34
品牌 Logo 应用领域
美国国家半导体 - NSC 计时器或实时时钟微控制器和处理器外围集成电路输出元件双倍数据速率
页数 文件大小 规格书
16页 271K
描述
Real Time Clock (RTC)

DP8573AV 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.32
其他特性:PRESCALED XTAL OSCILLATOR OUTPUT FOR RTC; POWER FAIL I/P FOR BUS LOCK-OUT外部数据总线宽度:8
信息访问方法:PARALLEL, DIRECT ADDRESS中断能力:Y
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.51 mm湿度敏感等级:2A
端子数量:28计时器数量:
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):245
电源:3/5 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Timer or RTC
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
最短时间:1/100 SECOND处于峰值回流温度下的最长时间:NOT SPECIFIED
易失性:YES宽度:11.51 mm
uPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCKBase Number Matches:1

DP8573AV 数据手册

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May 1993  
DP8573A Real Time Clock (RTC)  
General Description  
l
main supply to the battery supply.  
The DP8573A is intended for use in microprocessor based  
systems where information is required for multi-tasking, data  
logging or general time of day/date information. This device  
is implemented in low voltage silicon gate microCMOS tech-  
nology to provide low standby power in battery back-up en-  
vironments. The circuit’s architecture is such that it looks  
like a contiguous block of memory or I/O ports organized as  
one block of 32 bytes. This includes the Control Registers,  
the Clock Counters, the Alarm Compare RAM, and the Time  
Save RAM.  
V , internal circuitry will automatically switch from the  
CC  
The DP8573A’s interrupt structure provides three basic  
types of interrupts: Periodic, Alarm/Compare, and Power  
Fail. Interrupt mask and status registers enable the masking  
and easy determination of each interrupt.  
Features  
Y
Full function real time clock/calendar  
Ð 12/24 hour mode timekeeping  
Ð Day of week counter  
Ð Parallel resonant oscillator  
Time and date are maintained from 1/100 of a second to  
year and leap year in a BCD format, 12 or 24 hour modes.  
Day of week and day of month counters are provided. Time  
is controlled by an on-chip crystal oscillator requiring only  
the addition of the 32.768 kHz crystal and two capacitors.  
Y
Power fail features  
Ð Internal power supply switch to external battery  
Ð Power Supply Bus glitch protection  
Ð Automatic log of time into RAM at power failure  
Power failure logic and control functions have been integrat-  
ed on chip. This logic is used by the RTC to issue a power  
fail interrupt, and lock out the mP interface. The time power  
Y
On-chip interrupt structure  
Ð Periodic, alarm, and power fail interrupts  
l
fails may be logged into RAM automatically when V  
BB  
. Additionally, two supply pins are provided. When V  
V
CC  
BB  
Block Diagram  
TL/F/9981–1  
FIGURE 1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9981  
RRD-B30M75/Printed in U. S. A.  

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