Datasheet > DP84910-50

DP84910-50

更新时间： 2024-01-18 14:05:21

品牌	Logo	应用领域
美国国家半导体 - NSC		/
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32页	378K
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DP84910-50 数据手册

October 1994

DP84910 (-36/-50)

Integrated Read Channel

General Description

The DP84910 integrates most functions of the hard disk

read channel electronics onto a single 5V chip. It incorpo-

rates a pulse/servo detector, a programmable integrated

channel filter, a data synchronizer, a frequency synthesizer,

and a serial port interface. The chip receives data from a

read preamplifier, filters and peak detects the read pulses

for both data and embedded servo information and resyn-

chronizes the data with the system clock.

Independent power down control for all of the major blocks

within the chip is provided via three bits in the control

(SYNC PWR DN,

STH PWR DN

and

PD PWR DN) to manage power consumption. In addi-

tion, two pins (SLEEP and IDLE/SERVO) are available to

control power management. The sleep mode pin (SLEEP)

powers down all circuitry on the chip including the control

2 mA; the control register data must be reentered when

exiting this mode. The idle/servo mode pin (IDLE/SERVO)

toggles the device between the idle and servo modes. In the

idle mode, only the control register and pulse detector bias-

ing circuitry necessary for a quick recovery are active. In the

servo mode, the pulse detector portions needed for servo

detection are active as well as the control register. Less

than 15 ms is required for the pulse detector to recover from

the idle condition. The control register data is not lost when

The DP84910 is available in two versions, DP84910VHG-36

and DP84910VHG-50. The DP84910VHG-36 is specified to

operate over

a data rate range of 7.5 Mbits/sec to

36 Mbits/sec. The other version, DP84910VHG-50, will op-

erate over a data rate range of 13.7 Mbits/sec to 50 Mbits/

sec.

This device is specifically designed to address zoned data

rate applications. A channel filter with control register se-

lectable cutoff frequency and equalization is provided on-

chip. This eliminates the need for multiple external channel

filters and allows for greater flexibility in the selection of

zone frequencies. The frequency synthesizer provides cen-

ter frequency information for the data synchronizer and a

variable frequency write clock. There is no need for any off-

chip frequency setting components or DACs.

this pin is toggled. The pin can be rapidly toggled ( 15 ms)

to achieve average power consumption savings and will

keep the read/write head on track. Seventeen power and

ground pins are provided to isolate major functional blocks

and allow for independent supply voltage filtering, thus en-

hancing noise immunity.

(Continued)

A four-bank control register is included to control zoning

operations and configure general chip functions. At V

power-up the chip self-configures by presetting all bits in the

control register to predetermined operating setup condi-

tions.

TL/F/11777–1

FIGURE 1. DP84910 in a Typical Disk Drive System

MICROWIRE^TMis a trademark of National Semiconductor Corporation.

1996 National Semiconductor Corporation

TL/F/11777

RRD-B30M116/Printed in U. S. A.

http://www.national.com

12 3 4 5 6 7...32

中文翻译

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与DP84910-50相关器件

型号	品牌	获取价格	描述	数据表
DP84910VHG	NSC	获取价格	IC,DISK DATA SEP/SYNCHRONIZER,QFP,80PIN,PLASTIC
DP84910VHG-36	NSC	获取价格	Integrated Read Channel
DP84910VHG-50	NSC	获取价格	Integrated Read Channel
DP84920VHG	ETC	获取价格	Disk Read Data Processor
DP8496	NSC	获取价格	SCSI-2 Disk Data Controller
DP8496VF	NSC	获取价格	IC,DISK CONTROLLER,CMOS,QFP,100PIN
DP8497	NSC	获取价格	SCSI-2 Disk Data Controller
DP8497VF	NSC	获取价格	暂无描述
DP84T22	NSC	获取价格	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
DP84T22-25	NSC	获取价格	microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers

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