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DP8482AM

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DP8482AM 数据手册

April 1990

DP8482A 100k ECL to TTL Level Translator with Latch

General Description

This circuit translates ECL input levels to TTL output levels

Features

16-pin DIP or S.O.

and provides a fall-through latch. The TRI-STATE outputs

are designed to drive standard 50 pF loads. The strobe and

chip select inputs operate at ECL levels.

TRI-STATE outputs

ECL control inputs

8 ns typical propagation delay with 50 pF load

Outputs are TRI-STATE during power up/down for

glitch free operation

100k ECL input compatible

Logic and Connection Diagram

Truth Table

Dual-In-Line Package

STR

Hi-Z

high level (most positive)

low level (most negative)

don’t care

Order Number DP8482AJ, DP8482AM or DP8482AN

See NS Package Number J16A, N16A or M16B

TL/F/5863–1

Top View

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation

TL/F/5863

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6

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型号	品牌	获取价格	描述	数据表
DP8482AN	ETC	获取价格	ECL-to-TTL Translator
DP8482F	ETC	获取价格	ECL-to-TTL Translator
DP8482F/A+	ETC	获取价格	ECL-to-TTL Translator
DP8482J/A+	ETC	获取价格	ECL-to-TTL Translator
DP8482N	ETC	获取价格	ECL-to-TTL Translator
DP8482N/A+	ETC	获取价格	ECL-to-TTL Translator
DP8482N/B+	ETC	获取价格	ECL-to-TTL Translator
DP8483	NSC	获取价格	TTL to 100k ECL Level Translator with Latch
DP8483F	NSC	获取价格	TTL to 100k ECL Level Translator with Latch
DP8483F/A+	ETC	获取价格	TTL-to-ECL Translator