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DM74S299N PDF预览

DM74S299N

更新时间: 2024-11-30 22:35:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器存储触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 61K
描述
3-STATE 8-Bit Universal Shift/Storage Register

DM74S299N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.77
Is Samacsys:N其他特性:HOLD MODE
计数方向:BIDIRECTIONAL系列:S
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.075 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup:40000000 Hz位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):23 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:50 MHzBase Number Matches:1

DM74S299N 数据手册

 浏览型号DM74S299N的Datasheet PDF文件第2页浏览型号DM74S299N的Datasheet PDF文件第3页浏览型号DM74S299N的Datasheet PDF文件第4页浏览型号DM74S299N的Datasheet PDF文件第5页 
August 1986  
Revised May 2000  
DM74S299  
3-STATE 8-Bit Universal Shift/Storage Register  
General Description  
Features  
This Schottky TTL eight-bit universal register features mul-  
tiplexed inputs/outputs to achieve full eight bit data han-  
dling in a single 20-pin package. Two function-select inputs  
and two output-control inputs can be used to choose the  
modes of operation listed in the function table.  
Multiplexed inputs/outputs provide improved bit density  
Four modes of operation:  
Hold (Store)  
Shift Right  
Shift Left  
Load Data  
3-STATE outputs drive bus lines directly  
Can be cascaded for N-bit word lengths  
Operates with outputs enabled or at high Z  
Guaranteed shift (clock) frequency 50 MHz  
Typical power dissipation 700 mW  
Synchronous parallel loading is accomplished by taking  
both function-select lines, S0 and S1, HIGH. This places  
the 3-STATE outputs in a high-impedance state, which per-  
mits data that is applied on the input/output lines to be  
clocked into the register. Reading out of the register can be  
accomplished while the outputs are enabled in any mode.  
A direct overriding input is provided to clear the register  
whether the outputs are ENABLED or OFF.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S299N  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006485  
www.fairchildsemi.com  

DM74S299N 替代型号

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SN74S299N3 TI

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