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DM74S373WM PDF预览

DM74S373WM

更新时间: 2024-11-14 22:54:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 74K
描述
3-STATE Octal D-Type Transparent Latches

DM74S373WM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.48
Is Samacsys:N系列:S
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.02 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):190 mAProp。Delay @ Nom-Sup:16 ns
传播延迟(tpd):16 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

DM74S373WM 数据手册

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August 1986  
Revised May 2000  
DM74S373 DM74S374  
3-STATE Octal D-Type Transparent Latches  
and Edge-Triggered Flip-Flops  
Schmitt-trigger buffered inputs at the enable/clock lines  
simplify system design as ac and dc noise rejection is  
improved by typically 400 mV due to the input hysteresis. A  
buffered output control input can be used to place the eight  
outputs in either a normal logic state (HIGH or LOW logic  
levels) or a high-impedance state. In the high-impedance  
state the outputs neither load nor drive the bus lines signifi-  
cantly.  
General Description  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
The output control does not affect the internal operation of  
the latches or flip-flops. That is, the old data can be  
retained or new data can be entered even while the outputs  
are OFF.  
The eight latches of the DM74S373 are transparent D-type  
latches meaning that while the enable (G) is HIGH the Q  
outputs will follow the data (D) inputs. When the enable is  
taken LOW the output will be latched at the level of the  
data that was set up.  
Features  
Choice of 8 latches or 8 D-type flip-flops in a single  
package  
The eight flip-flops of the DM74S374 are edge-triggered D-  
type flip-flops. On the positive transition of the clock, the Q  
outputs will be set to the logic states that were set up at the  
D inputs.  
3-STATE bus-driving outputs  
Full parallel-access for loading  
Buffered control inputs  
P-N-P input reduce D-C loading on data lines  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S373WM  
DM74S373N  
DM74S374WM  
DM74S374N  
M20B  
N20A  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
DM74S374N  
DM74S373N  
© 2000 Fairchild Semiconductor Corporation  
DS006486  
www.fairchildsemi.com  

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