DM74S373

更新时间： 2024-11-14 22:54:35

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		锁存器
页数	文件大小	规格书
7页	74K
描述
3-STATE Octal D-Type Transparent Latches

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

DM74S373 数据手册

August 1986

Revised May 2000

DM74S373 • DM74S374

3-STATE Octal D-Type Transparent Latches

and Edge-Triggered Flip-Flops

Schmitt-trigger buffered inputs at the enable/clock lines

simplify system design as ac and dc noise rejection is

improved by typically 400 mV due to the input hysteresis. A

buffered output control input can be used to place the eight

outputs in either a normal logic state (HIGH or LOW logic

levels) or a high-impedance state. In the high-impedance

state the outputs neither load nor drive the bus lines signifi-

cantly.

General Description

These 8-bit registers feature totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low-impedance loads. The high-impedance state and

increased high-logic-level drive provide these registers with

the capability of being connected directly to and driving the

bus lines in a bus-organized system without need for inter-

face or pull-up components. They are particularly attractive

for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

The output control does not affect the internal operation of

the latches or flip-flops. That is, the old data can be

retained or new data can be entered even while the outputs

are OFF.

The eight latches of the DM74S373 are transparent D-type

latches meaning that while the enable (G) is HIGH the Q

outputs will follow the data (D) inputs. When the enable is

taken LOW the output will be latched at the level of the

data that was set up.

Features

■ Choice of 8 latches or 8 D-type flip-flops in a single

package

The eight flip-flops of the DM74S374 are edge-triggered D-

type flip-flops. On the positive transition of the clock, the Q

outputs will be set to the logic states that were set up at the

D inputs.

■ 3-STATE bus-driving outputs

■ Full parallel-access for loading

■ Buffered control inputs

■ P-N-P input reduce D-C loading on data lines

Ordering Code:

Order Number Package Number

Package Description

DM74S373WM

DM74S373N

DM74S374WM

DM74S374N

M20B

N20A

M20B

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

DM74S374N

DM74S373N

DS006486

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

下载PDF

与DM74S373相关器件

型号	品牌	获取价格	描述	数据表
DM74S373J/A+	ETC	获取价格	8-Bit D-Type Latch
DM74S373N	FAIRCHILD	获取价格	3-STATE Octal D-Type Transparent Latches
DM74S373N/A+	ETC	获取价格	8-Bit D-Type Latch
DM74S373N/B+	ETC	获取价格	8-Bit D-Type Latch
DM74S373WM	FAIRCHILD	获取价格	3-STATE Octal D-Type Transparent Latches
DM74S373WMX	FAIRCHILD	获取价格	8-Bit D-Type Latch
DM74S374J/A+	ETC	获取价格	Octal D-Type Flip-Flop
DM74S374N	FAIRCHILD	获取价格	3-STATE Octal D-Type Transparent Latches
DM74S374N/A+	ETC	获取价格	Octal D-Type Flip-Flop
DM74S374N/B+	ETC	获取价格	Octal D-Type Flip-Flop

与DM74S373相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

7
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

4
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

30
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

13

产品中心

服务支持

精选活动

关于我们

帮助中心

DM74S373

DM74S373 数据手册

与DM74S373相关器件

与DM74S373相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DM74S373

DM74S373 数据手册

与DM74S373相关器件

与DM74S373相关文章

您还可以找

您在本页遇到什么问题？