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DM74LS93 PDF预览

DM74LS93

更新时间: 2024-11-26 05:09:51
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美国国家半导体 - NSC 计数器
页数 文件大小 规格书
10页 134K
描述
Decade and Binary Counters

DM74LS93 数据手册

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June 1989  
DM74LS90/DM74LS93  
Decade and Binary Counters  
General Description  
Each of these monolithic counters contains four master-  
slave flip-flops and additional gating to provide a divide-by-  
two counter and a three-stage binary counter for which the  
count cycle length is divide-by-five for the ’LS90 and divide-  
by-eight for the ’LS93.  
count pulses are applied to input A and the outputs are as  
described in the appropriate truth table. A symmetrical di-  
vide-by-ten count can be obtained from the ’LS90 counters  
by connecting the Q output to the A input and applying the  
D
input count to the B input which gives a divide-by-ten square  
wave at output Q .  
A
All of these counters have a gated zero reset and the LS90  
also has gated set-to-nine inputs for use in BCD nine’s com-  
plement applications.  
Features  
Y
Typical power dissipation 45 mW  
To use their maximum count length (decade or four bit bina-  
ry), the B input is connected to the Q output. The input  
A
Y
Count frequency 42 MHz  
Connection Diagrams (Dual-In-Line Packages)  
TL/F/6381–1  
Order Number DM74LS90M or DM74LS90N  
See NS Package Number M14A or N14A  
TL/F/6381–2  
Order Number DM74LS93M or DM74LS93N  
See NS Package Number M14A or N14A  
C
1995 National Semiconductor Corporation  
TL/F/6381  
RRD-B30M105/Printed in U. S. A.  

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