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DM74LS93N PDF预览

DM74LS93N

更新时间: 2024-11-25 23:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 134K
描述
Decade and Binary Counters

DM74LS93N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.6
其他特性:DIVIDE BY 2 AND DIVIDE BY 8 FUNCTIONS计数方向:UP
系列:LSJESD-30 代码:R-PDIP-T14
JESD-609代码:e0长度:19.18 mm
负载电容(CL):15 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.008 A工作模式:ASYNCHRONOUS
位数:3功能数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):15 mA传播延迟(tpd):51 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:16 MHzBase Number Matches:1

DM74LS93N 数据手册

 浏览型号DM74LS93N的Datasheet PDF文件第2页浏览型号DM74LS93N的Datasheet PDF文件第3页浏览型号DM74LS93N的Datasheet PDF文件第4页浏览型号DM74LS93N的Datasheet PDF文件第5页浏览型号DM74LS93N的Datasheet PDF文件第6页浏览型号DM74LS93N的Datasheet PDF文件第7页 
June 1989  
DM74LS90/DM74LS93  
Decade and Binary Counters  
General Description  
Each of these monolithic counters contains four master-  
slave flip-flops and additional gating to provide a divide-by-  
two counter and a three-stage binary counter for which the  
count cycle length is divide-by-five for the ’LS90 and divide-  
by-eight for the ’LS93.  
count pulses are applied to input A and the outputs are as  
described in the appropriate truth table. A symmetrical di-  
vide-by-ten count can be obtained from the ’LS90 counters  
by connecting the Q output to the A input and applying the  
D
input count to the B input which gives a divide-by-ten square  
wave at output Q .  
A
All of these counters have a gated zero reset and the LS90  
also has gated set-to-nine inputs for use in BCD nine’s com-  
plement applications.  
Features  
Y
Typical power dissipation 45 mW  
To use their maximum count length (decade or four bit bina-  
ry), the B input is connected to the Q output. The input  
A
Y
Count frequency 42 MHz  
Connection Diagrams (Dual-In-Line Packages)  
TL/F/6381–1  
Order Number DM74LS90M or DM74LS90N  
See NS Package Number M14A or N14A  
TL/F/6381–2  
Order Number DM74LS93M or DM74LS93N  
See NS Package Number M14A or N14A  
C
1995 National Semiconductor Corporation  
TL/F/6381  
RRD-B30M105/Printed in U. S. A.  

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