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DM74LS175SJX PDF预览

DM74LS175SJX

更新时间: 2024-09-15 23:47:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 76K
描述
Quad D-Type Flip-Flop

DM74LS175SJX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.33
系列:LSJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:10.2 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:25000000 Hz
最大I(ol):0.008 A位数:4
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):18 mA
传播延迟(tpd):36 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.3 mm最小 fmax:30 MHz
Base Number Matches:1

DM74LS175SJX 数据手册

 浏览型号DM74LS175SJX的Datasheet PDF文件第2页浏览型号DM74LS175SJX的Datasheet PDF文件第3页浏览型号DM74LS175SJX的Datasheet PDF文件第4页浏览型号DM74LS175SJX的Datasheet PDF文件第5页浏览型号DM74LS175SJX的Datasheet PDF文件第6页浏览型号DM74LS175SJX的Datasheet PDF文件第7页 
August 1992  
Revised April 2000  
DM74LS174 • DM74LS175  
Hex/Quad D-Type Flip-Flops with Clear  
General Description  
Features  
These positive-edge-triggered flip-flops utilize TTL circuitry  
to implement D-type flip-flop logic. All have a direct clear  
input, and the quad (175) versions feature complementary  
outputs from each flip-flop.  
DM74LS174 contains six flip-flops with single-rail  
outputs  
DM74LS175 contains four flip-flops with double-rail  
outputs  
Information at the D inputs meeting the setup time require-  
ments is transferred to the Q outputs on the positive-going  
edge of the clock pulse. Clock triggering occurs at a partic-  
ular voltage level and is not directly related to the transition  
time of the positive-going pulse. When the clock input is at  
either the HIGH or LOW level, the D input signal has no  
effect at the output.  
Buffered clock and direct clear inputs  
Individual data input to each flip-flop  
Applications include:  
Buffer/storage registers  
Shift registers  
Pattern generators  
Typical clock frequency 40 MHz  
Typical power dissipation per flip-flop 14 mW  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS174M  
DM74LS174SJ  
DM74LS174N  
DM74LS175M  
DM74LS175SJ  
DM74LS175N  
M16A  
M16D  
N16E  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
DM74LS174  
DM74LS175  
© 2000 Fairchild Semiconductor Corporation  
DS006404  
www.fairchildsemi.com  

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