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DM74LS138CW PDF预览

DM74LS138CW

更新时间： 2024-11-11 13:02:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解码器解复用器
页数 文件大小 规格书
7页 85K
描述
Decoder/Driver, LS Series, Inverted Output, TTL, WAFER

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DM74LS138CW 技术参数

生命周期：Obsolete零件包装代码：WAFER
包装说明：WAFERReach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.71Is Samacsys：N
系列：LSJESD-30 代码：X-XUUC-N
逻辑集成电路类型：OTHER DECODER/DRIVER功能数量：1
最高工作温度：70 °C最低工作温度：
输出极性：INVERTED封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：UNSPECIFIED
封装形式：UNCASED CHIP传播延迟（tpd）：40 ns
认证状态：Not Qualified最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子形式：NO LEAD
端子位置：UPPERBase Number Matches：1

DM74LS138CW 数据手册

 浏览型号DM74LS138CW的Datasheet PDF文件第2页浏览型号DM74LS138CW的Datasheet PDF文件第3页浏览型号DM74LS138CW的Datasheet PDF文件第4页浏览型号DM74LS138CW的Datasheet PDF文件第5页浏览型号DM74LS138CW的Datasheet PDF文件第6页浏览型号DM74LS138CW的Datasheet PDF文件第7页 
August 1986  
Revised March 2000  
DM74LS138 • DM74LS139  
Decoder/Demultiplexer  
General Description  
Features  
These Schottky-clamped circuits are designed to be used  
in high-performance memory-decoding or data-routing  
applications, requiring very short propagation delay times.  
In high-performance memory systems these decoders can  
be used to minimize the effects of system decoding. When  
used with high-speed memories, the delay times of these  
decoders are usually less than the typical access time of  
the memory. This means that the effective system delay  
introduced by the decoder is negligible.  
■ Designed specifically for high speed:  
Memory decoders  
Data transmission systems  
■ DM74LS138 3-to-8-line decoders incorporates 3 enable  
inputs to simplify cascading and/or data reception  
■ DM74LS139 contains two fully independent 2-to-4-line  
decoders/demultiplexers  
■ Schottky clamped for high performance  
■ Typical propagation delay (3 levels of logic)  
DM74LS138 21 ns  
The DM74LS138 decodes one-of-eight lines, based upon  
the conditions at the three binary select inputs and the  
three enable inputs. Two active-low and one active-high  
enable inputs reduce the need for external gates or invert-  
ers when expanding. A 24-line decoder can be imple-  
mented with no external inverters, and a 32-line decoder  
requires only one inverter. An enable input can be used as  
a data input for demultiplexing applications.  
DM74LS139 21 ns  
■ Typical power dissipation  
DM74LS138 32 mW  
DM74LS139 34 mW  
The DM74LS139 comprises two separate two-line-to-four-  
line decoders in a single package. The active-low enable  
input can be used as a data line in demultiplexing applica-  
tions.  
All of these decoders/demultiplexers feature fully buffered  
inputs, presenting only one normalized load to its driving  
circuit. All inputs are clamped with high-performance  
Schottky diodes to suppress line-ringing and simplify sys-  
tem design.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS138M  
DM74LS138SJ  
DM74LS138N  
DM74LS139M  
DM74LS139SJ  
DM74LS139N  
M16A  
M16D  
N16E  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006391  
www.fairchildsemi.com  
1234567

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