DM74LS139SJ

更新时间： 2024-09-20 23:00:43

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		解码器解复用器
页数	文件大小	规格书
7页	85K
描述
Decoder/Demultiplexer

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中文翻译

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数据手册

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DM74LS139SJ 数据手册

August 1986

Revised March 2000

DM74LS138 • DM74LS139

Decoder/Demultiplexer

General Description

Features

These Schottky-clamped circuits are designed to be used

in high-performance memory-decoding or data-routing

applications, requiring very short propagation delay times.

In high-performance memory systems these decoders can

be used to minimize the effects of system decoding. When

used with high-speed memories, the delay times of these

decoders are usually less than the typical access time of

the memory. This means that the effective system delay

introduced by the decoder is negligible.

■ Designed specifically for high speed:

Memory decoders

Data transmission systems

■ DM74LS138 3-to-8-line decoders incorporates 3 enable

inputs to simplify cascading and/or data reception

■ DM74LS139 contains two fully independent 2-to-4-line

decoders/demultiplexers

■ Schottky clamped for high performance

■ Typical propagation delay (3 levels of logic)

DM74LS138 21 ns

The DM74LS138 decodes one-of-eight lines, based upon

the conditions at the three binary select inputs and the

three enable inputs. Two active-low and one active-high

enable inputs reduce the need for external gates or invert-

ers when expanding. A 24-line decoder can be imple-

mented with no external inverters, and a 32-line decoder

requires only one inverter. An enable input can be used as

a data input for demultiplexing applications.

DM74LS139 21 ns

■ Typical power dissipation

DM74LS138 32 mW

DM74LS139 34 mW

The DM74LS139 comprises two separate two-line-to-four-

line decoders in a single package. The active-low enable

input can be used as a data line in demultiplexing applica-

tions.

All of these decoders/demultiplexers feature fully buffered

inputs, presenting only one normalized load to its driving

circuit. All inputs are clamped with high-performance

Schottky diodes to suppress line-ringing and simplify sys-

tem design.

Ordering Code:

Order Number Package Number

Package Description

DM74LS138M

DM74LS138SJ

DM74LS138N

DM74LS139M

DM74LS139SJ

DM74LS139N

M16A

M16D

N16E

M16A

M16D

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS006391

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

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与DM74LS139SJ相关器件

型号	品牌	获取价格	描述	数据表
DM74LS139SJX	FAIRCHILD	获取价格	2-To-4-Line Demultiplexer
DM74LS139W	NSC	获取价格	Decoders/Demultiplexers
DM74LS13J	ETC	获取价格	Dual 4-input NAND Gate
DM74LS13J/A+	ETC	获取价格	Dual 4-input NAND Gate
DM74LS13M	NSC	获取价格	DUAL 4-INPUT SCHMITT TRIGGER
DM74LS13N	NSC	获取价格	DUAL 4-INPUT SCHMITT TRIGGER
DM74LS13N/A+	ETC	获取价格	Dual 4-input NAND Gate
DM74LS13N/B+	ETC	获取价格	Dual 4-input NAND Gate
DM74LS13W	ETC	获取价格	Dual 4-input NAND Gate
DM74LS14	FAIRCHILD	获取价格	Hex Inverter with Schmitt Trigger Inputs

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