DM74LS139W

更新时间： 2024-11-30 23:00:43

品牌	Logo	应用领域
美国国家半导体 - NSC		解码器解复用器
页数	文件大小	规格书
8页	167K
描述
Decoders/Demultiplexers

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中文翻译

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数据手册

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DM74LS139W 数据手册

June 1989

54LS138/DM54LS138/DM74LS138,

54LS139/DM54LS139/DM74LS139

Decoders/Demultiplexers

General Description

These Schottky-clamped circuits are designed to be used in

high-performance memory-decoding or data-routing appli-

cations, requiring very short propagation delay times. In

high-performance memory systems these decoders can be

used to minimize the effects of system decoding. When

used with high-speed memories, the delay times of these

decoders are usually less than the typical access time of the

memory. This means that the effective system delay intro-

duced by the decoder is negligible.

Schottky diodes to suppress line-ringing and simplify system

design.

Features

Designed specifically for high speed:

Memory decoders

Data transmission systems

LS138 3-to-8-line decoders incorporates 3 enable in-

puts to simplify cascading and/or data reception

The LS138 decodes one-of-eight lines, based upon the con-

ditions at the three binary select inputs and the three enable

inputs. Two active-low and one active-high enable inputs

reduce the need for external gates or inverters when ex-

panding. A 24-line decoder can be implemented with no ex-

ternal inverters, and a 32-line decoder requires only one

inverter. An enable input can be used as a data input for

demultiplexing applications.

LS139 contains two fully independent 2-to-4-line decod-

ers/demultiplexers

Schottky clamped for high performance

Typical propagation delay (3 levels of logic)

LS138 21 ns

LS139 21 ns

Typical power dissipation

LS138 32 mW

LS139 34 mW

The LS139 comprises two separate two-line-to-four-line de-

coders in a single package. The active-low enable input can

be used as a data line in demultiplexing applications.

Alternate

Military/Aerospace

devices

(54LS138,

54LS139) are available. Contact a National Semicon-

ductor Sales Office/Distributor for specifications.

All of these decoders/demultiplexers feature fully buffered

inputs, presenting only one normalized load to its driving

circuit. All inputs are clamped with high-performance

Connection Diagrams

Dual-in-Line Package

TL/F/6391–1

Order Number 54LS138DMQB, 54LS138FMQB,

54LS138LMQB, DM54LS138J, DM54LS138W,

DM74LS138M or DM74LS138N

TL/F/6391–2

Order Number 54LS139DMQB, 54LS139FMQB,

54LS139LMQB, DM54LS139J, DM54LS139W,

DM74LS139M or DM74LS139N

See NS Package Number E20A, J16A,

M16A, N16E or W16A

See NS Package Number E20A, J16A,

M16A, N16E or W16A

1995 National Semiconductor Corporation

TL/F/6391

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7 8

中文翻译

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与DM74LS139W相关器件

型号	品牌	获取价格	描述	数据表
DM74LS13J	ETC	获取价格	Dual 4-input NAND Gate
DM74LS13J/A+	ETC	获取价格	Dual 4-input NAND Gate
DM74LS13M	NSC	获取价格	DUAL 4-INPUT SCHMITT TRIGGER
DM74LS13N	NSC	获取价格	DUAL 4-INPUT SCHMITT TRIGGER
DM74LS13N/A+	ETC	获取价格	Dual 4-input NAND Gate
DM74LS13N/B+	ETC	获取价格	Dual 4-input NAND Gate
DM74LS13W	ETC	获取价格	Dual 4-input NAND Gate
DM74LS14	FAIRCHILD	获取价格	Hex Inverter with Schmitt Trigger Inputs
DM74LS14	NSC	获取价格	Hex Inverters with Schmitt Trigger Inputs
DM74LS14J	NSC	获取价格	IC,LOGIC GATE,HEX INVERTER,LS-TTL,DIP,14PIN,CERAMIC

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