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DM74LS151J PDF预览

DM74LS151J

更新时间: 2024-11-09 23:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器
页数 文件大小 规格书
6页 143K
描述
Data Selector/Multiplexer

DM74LS151J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:compliant
风险等级:5.92JESD-30 代码:R-XDIP-T16
JESD-609代码:e0逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.008 A功能数量:1
输入次数:8端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
最大电源电流(ICC):10 mAProp。Delay @ Nom-Sup:43 ns
认证状态:Not Qualified子类别:Multiplexer/Demultiplexers
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL

DM74LS151J 数据手册

 浏览型号DM74LS151J的Datasheet PDF文件第2页浏览型号DM74LS151J的Datasheet PDF文件第3页浏览型号DM74LS151J的Datasheet PDF文件第4页浏览型号DM74LS151J的Datasheet PDF文件第5页浏览型号DM74LS151J的Datasheet PDF文件第6页 
June 1989  
54LS151/DM54LS151/DM74LS151  
Data Selector/Multiplexer  
General Description  
Features  
Y
Y
Y
Y
Y
Select one-of-eight data lines  
This data selector/multiplexer contains full on-chip decod-  
ing to select the desired data source. The ’LS151 selects  
one-of-eight data sources. The ’LS151 has a strobe input  
which must be at a low logic level to enable these devices.  
A high level at the strobe forces the W output high, and the  
Y output low.  
Performs parallel-to-serial conversion  
Permits multiplexing from N lines to one line  
Also for use as Boolean function generator  
Typical average propagation delay time data input to W  
output 12.5 ns  
The ’LS151 features complementary W and Y outputs.  
Y
Y
Typical power dissipation 30 mW  
Alternate Military/Aerospace device (54LS151) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6392–1  
Order Number 54LS151DMQB, 54LS151FMQB, 54LS151LMQB,  
DM54LS151J, DM54LS151W, DM74LS151M or DM74LS151N  
See NS Package Number E20A, J16A, M16A, N16E or W16A  
Truth Table  
Inputs  
A
Outputs  
Select  
B
Strobe  
S
Y
W
C
X
L
X
L
X
L
H
L
L
L
L
L
L
L
L
L
H
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
e
e
e
Don’t Care  
H
High Level, L  
Low Level, X  
e
D0, D1...D7  
the level of the respective D input  
C
1995 National Semiconductor Corporation  
TL/F/6392  
RRD-B30M105/Printed in U. S. A.  

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