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DM74LS153 PDF预览

DM74LS153

更新时间: 2024-11-30 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 复用器
页数 文件大小 规格书
5页 55K
描述
Dual 1-of-4 Line Data Selectors/Multiplexers

DM74LS153 数据手册

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August 1986  
Revised March 2000  
DM74LS153  
Dual 1-of-4 Line Data Selectors/Multiplexers  
General Description  
Features  
Each of these data selectors/multiplexers contains invert-  
ers and drivers to supply fully complementary, on-chip,  
binary decoding data selection to the AND-OR-invert  
gates. Separate strobe inputs are provided for each of the  
two four-line sections.  
Permits multiplexing from N lines to 1 line  
Performs at parallel-to-serial conversion  
Strobe (enable) line provided for cascading  
(N lines to n lines)  
High fan-out, low impedance, totem pole outputs  
Typical average propagation delay times  
From data  
14 ns  
From strobe 19 ns  
From select 22 ns  
Typical power dissipation 31 mW  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS153M  
DM74LS153N  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Select  
Inputs  
Data Inputs  
Strobe  
Output  
B
X
L
A
X
L
C0  
X
L
C1  
X
X
X
L
C2  
X
X
X
X
X
L
C3  
X
X
X
X
X
X
X
L
G
H
L
L
L
L
L
L
L
L
Y
L
L
L
L
H
X
X
X
X
X
X
H
L
L
H
H
L
L
H
X
X
X
X
H
L
H
H
H
H
L
H
X
X
H
L
H
H
H
H
Select inputs A and B are common to both sections.  
H = HIGH Level  
L = LOW Level  
X = Don't Care  
© 2000 Fairchild Semiconductor Corporation  
DS006393  
www.fairchildsemi.com  

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