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DM74LS153J PDF预览

DM74LS153J

更新时间: 2024-11-30 23:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器
页数 文件大小 规格书
6页 145K
描述
Dual 4-Line to 1-Line Data Selectors/Multiplexers

DM74LS153J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:compliant
风险等级:5.87JESD-30 代码:R-XDIP-T16
JESD-609代码:e0逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.008 A功能数量:2
输入次数:4端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
最大电源电流(ICC):10 mAProp。Delay @ Nom-Sup:38 ns
认证状态:Not Qualified子类别:Multiplexer/Demultiplexers
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

DM74LS153J 数据手册

 浏览型号DM74LS153J的Datasheet PDF文件第2页浏览型号DM74LS153J的Datasheet PDF文件第3页浏览型号DM74LS153J的Datasheet PDF文件第4页浏览型号DM74LS153J的Datasheet PDF文件第5页浏览型号DM74LS153J的Datasheet PDF文件第6页 
June 1989  
54LS153/DM54LS153/DM74LS153  
Dual 4-Line to 1-Line Data Selectors/Multiplexers  
Y
Strobe (enable) line provided for cascading (N lines to  
n lines)  
General Description  
Each of these data selectors/multiplexers contains invert-  
ers and drivers to supply fully complementary, on-chip, bina-  
ry decoding data selection to the AND-OR-invert gates.  
Separate strobe inputs are provided for each of the two  
four-line sections.  
Y
Y
High fan-out, low impedance, totem pole outputs  
Typical average propagation delay times  
Ð From data 14 ns  
Ð From strobe 19 ns  
Ð From select 22 ns  
Y
Y
Typical power dissipation 31 mW  
Alternate Military/Aerospace device (54LS153) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
Features  
Y
Permits multiplexing from N lines to 1 line  
Y
Performs at parallel-to-serial conversion  
Connection Diagram  
Dual-In-Line Package  
Order Number 54LS153DMQB, 54LS153FMQB,  
54LS153LMQB, DM54LS153J, DM54LS153W,  
DM74LS153M or DM74LS153N  
See NS Package Number E20A, J16A, M16A,  
N16E or W16A  
TL/F/6393–1  
Logic Diagram  
Function Table  
Select  
Data Inputs  
Strobe  
G
Output  
Y
Inputs  
B
A
C0  
C1  
C2  
C3  
X
L
X
L
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
X
X
X
X
X
X
H
L
L
H
H
L
L
H
X
X
X
X
H
L
H
H
H
H
L
H
X
X
H
L
H
H
H
H
Select inputs A and B are common to both sections.  
e
e
e
Low Level, X Don’t Care  
H
High Level, L  
TL/F/6393–2  
C
1995 National Semiconductor Corporation  
TL/F/6393  
RRD-B30M105/Printed in U. S. A.  

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