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DM74ALS576AN_NL PDF预览

DM74ALS576AN_NL

更新时间: 2024-11-04 19:57:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 69K
描述
Bus Driver, ALS Series, 1-Func, 8-Bit, Inverted Output, TTL, PDIP20, 0.300 INCH, PLASTIC, MS-001, DIP-20

DM74ALS576AN_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:compliant
风险等级:5.52系列:ALS
JESD-30 代码:R-PDIP-T20JESD-609代码:e3
长度:26.075 mm逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:30000000 Hz最大I(ol):0.024 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:RAIL
峰值回流温度(摄氏度):NOT APPLICABLE电源:5 V
最大电源电流(ICC):30 mA传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT APPLICABLE
触发器类型:POSITIVE EDGE宽度:7.62 mm
Base Number Matches:1

DM74ALS576AN_NL 数据手册

 浏览型号DM74ALS576AN_NL的Datasheet PDF文件第2页浏览型号DM74ALS576AN_NL的Datasheet PDF文件第3页浏览型号DM74ALS576AN_NL的Datasheet PDF文件第4页浏览型号DM74ALS576AN_NL的Datasheet PDF文件第5页浏览型号DM74ALS576AN_NL的Datasheet PDF文件第6页浏览型号DM74ALS576AN_NL的Datasheet PDF文件第7页 
October 1986  
Revised July 2004  
DM74ALS576A  
Octal D-Type Edge-Triggered Flip-Flop  
with 3-STATE Outputs  
General Description  
Features  
Switching specifications at 50 pF  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
3-STATE buffer-type outputs drive bus lines directly  
The eight flip-flops of the DM74ALS576A are edge-trig-  
gered inverting D-type flip-flops. On the positive transition  
of the clock, the Q outputs will be set to the complement of  
the logic states that were set up at the D inputs.  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the flip-flops. That is, the old data can be retained or new  
data can be entered even while the outputs are OFF.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
DM74ALS576AWM  
(Note 1)  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
DM74ALS576SJX  
DM74ALS576AN  
M20D  
N20A  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Note 1: Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2004 Fairchild Semiconductor Corporation  
DS006228  
www.fairchildsemi.com  

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