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DM74ALS576SJX PDF预览

DM74ALS576SJX

更新时间: 2024-11-19 03:06:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 74K
描述
Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs

DM74ALS576SJX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:compliant
风险等级:5.34系列:ALS
JESD-30 代码:R-PDSO-G20长度:12.6 mm
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:30000000 Hz
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):30 mA
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.3 mm
Base Number Matches:1

DM74ALS576SJX 数据手册

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October 1986  
Revised July 2004  
DM74ALS576A  
Octal D-Type Edge-Triggered Flip-Flop  
with 3-STATE Outputs  
General Description  
Features  
Switching specifications at 50 pF  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
3-STATE buffer-type outputs drive bus lines directly  
The eight flip-flops of the DM74ALS576A are edge-trig-  
gered inverting D-type flip-flops. On the positive transition  
of the clock, the Q outputs will be set to the complement of  
the logic states that were set up at the D inputs.  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the flip-flops. That is, the old data can be retained or new  
data can be entered even while the outputs are OFF.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
DM74ALS576AWM  
(Note 1)  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
DM74ALS576SJX  
DM74ALS576AN  
M20D  
N20A  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Note 1: Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2004 Fairchild Semiconductor Corporation  
DS006228  
www.fairchildsemi.com  

DM74ALS576SJX 替代型号

型号 品牌 替代类型 描述 数据表
DM74ALS576AWMX FAIRCHILD

完全替代

Octal D-Type Flip-Flop
DM74ALS576AWM FAIRCHILD

完全替代

Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs
SN74ALS576BDWR TI

类似代替

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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