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DM74ALS580AN_NL PDF预览

DM74ALS580AN_NL

更新时间： 2024-11-19 13:07:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
6页 61K
描述
Bus Driver, ALS Series, 1-Func, 8-Bit, Inverted Output, TTL, PDIP20, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-20

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DM74ALS580AN_NL 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknown风险等级：5.73
系列：ALSJESD-30 代码：R-PDIP-T20
JESD-609代码：e3长度：26.075 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：18 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

DM74ALS580AN_NL 数据手册

 浏览型号DM74ALS580AN_NL的Datasheet PDF文件第2页浏览型号DM74ALS580AN_NL的Datasheet PDF文件第3页浏览型号DM74ALS580AN_NL的Datasheet PDF文件第4页浏览型号DM74ALS580AN_NL的Datasheet PDF文件第5页浏览型号DM74ALS580AN_NL的Datasheet PDF文件第6页 
April 1984  
Revised February 2000  
DM74ALS580A  
Octal D-Type Transparent Latch with 3-STATE Outputs  
General Description  
Features  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
■ Switching specifications at 50 pF  
■ Switching specifications guaranteed over full tempera-  
ture and VCC range  
■ Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
■ 3-STATE buffer-type outputs drive bus lines directly  
The eight inverting latches of the DM74ALS580A are trans-  
parent D-type latches. While the enable (G) is HIGH the Q  
outputs will follow the complement of the data (D) inputs.  
When the enable is taken LOW the output will be latched at  
the complement of the level of the data that was set up.  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the latches. That is, the old data can be retained or new  
data can be entered even while the outputs are OFF.  
Ordering Code:  
Order Number  
DM74ALS580AWM  
DM74ALS580AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
N20A  
Devises also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006229  
www.fairchildsemi.com  
123456

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DM74ALS580AWM FAIRCHILD

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 		Octal D-Type Transparent Latch with 3-STATE Outputs
DM74ALS580AWM/A+ ETC

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 		8-Bit D-Type Latch
DM74ALS580AWM/B+ ETC

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 		8-Bit D-Type Latch
DM74ALS580AWMX FAIRCHILD

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 		Bus Driver, ALS Series, 1-Func, 8-Bit, Inverted Output, TTL, PDSO20, 0.300 INCH, MS-013, S
DM74ALS580J/A+ ETC

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 		8-Bit D-Type Latch
DM74ALS580N NSC

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 		IC,LATCH,SINGLE,8-BIT,ALS-TTL,DIP,20PIN,PLASTIC
DM74ALS580N/A+ ETC

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 		8-Bit D-Type Latch
DM74ALS580N/B+ ETC

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 		8-Bit D-Type Latch
DM74ALS590M TI

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 		ALS SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PDSO16, SOP-16
DM74ALS590M/A+ ETC

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 		Asynchronous Up Counter

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