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DM74ALS576AWMX_NL PDF预览

DM74ALS576AWMX_NL

更新时间： 2024-11-19 19:57:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 69K
描述
Bus Driver, ALS Series, 1-Func, 8-Bit, Inverted Output, TTL, PDSO20, 0.300 INCH, MS-013, SOIC-20

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DM74ALS576AWMX_NL 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP20,.4
针数：20Reach Compliance Code：compliant
风险等级：5.34系列：ALS
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：12.8 mm逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：30000000 Hz最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：30 mA
传播延迟（tpd）：14 ns认证状态：Not Qualified
座面最大高度：2.642 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mmBase Number Matches：1

DM74ALS576AWMX_NL 数据手册

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October 1986  
Revised July 2004  
DM74ALS576A  
Octal D-Type Edge-Triggered Flip-Flop  
with 3-STATE Outputs  
General Description  
Features  
■ Switching specifications at 50 pF  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
■ Switching specifications guaranteed over full tempera-  
ture and VCC range  
■ Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
■ 3-STATE buffer-type outputs drive bus lines directly  
The eight flip-flops of the DM74ALS576A are edge-trig-  
gered inverting D-type flip-flops. On the positive transition  
of the clock, the Q outputs will be set to the complement of  
the logic states that were set up at the D inputs.  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the flip-flops. That is, the old data can be retained or new  
data can be entered even while the outputs are OFF.  
Ordering Code:  
Order Number  
Package Number  
Package Description  
DM74ALS576AWM  
(Note 1)  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
DM74ALS576SJX  
DM74ALS576AN  
M20D  
N20A  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Note 1: Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2004 Fairchild Semiconductor Corporation  
DS006228  
www.fairchildsemi.com  
1234567

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与DM74ALS576AWMX_NL相关器件

型号 品牌 获取价格 描述 数据表
DM74ALS576J/A+ NSC

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 		IC,FLIP-FLOP,OCTAL,D TYPE,ALS-TTL,DIP,20PIN,CERAMIC
DM74ALS576N NSC

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 		IC,FLIP-FLOP,OCTAL,D TYPE,ALS-TTL,DIP,20PIN,PLASTIC
DM74ALS576N/A+ ETC

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 		Octal D-Type Flip-Flop
DM74ALS576N/B+ NSC

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 		IC,FLIP-FLOP,OCTAL,D TYPE,ALS-TTL,DIP,20PIN,PLASTIC
DM74ALS576SJX FAIRCHILD

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 		Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs
DM74ALS580A FAIRCHILD

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 		Octal D-Type Transparent Latch with 3-STATE Outputs
DM74ALS580AJ NSC

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 		IC,LATCH,SINGLE,8-BIT,ALS-TTL,DIP,20PIN,CERAMIC
DM74ALS580AN FAIRCHILD

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 		Octal D-Type Transparent Latch with 3-STATE Outputs
DM74ALS580AN/A+ NSC

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 		IC,LATCH,SINGLE,8-BIT,ALS-TTL,DIP,20PIN,PLASTIC
DM74ALS580AN/B+ NSC

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 		IC,LATCH,SINGLE,8-BIT,ALS-TTL,DIP,20PIN,PLASTIC

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