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DM74ALS174MX_NL PDF预览

DM74ALS174MX_NL

更新时间: 2024-09-16 20:06:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 72K
描述
D Flip-Flop, ALS Series, 6-Func, Positive Edge Triggered, 1-Bit, True Output, TTL, PDSO16, 0.150 INCH, MS-012, SOIC-16

DM74ALS174MX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.26
系列:ALSJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:50000000 Hz
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:6
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):19 mA传播延迟(tpd):17 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:50 MHzBase Number Matches:1

DM74ALS174MX_NL 数据手册

 浏览型号DM74ALS174MX_NL的Datasheet PDF文件第2页浏览型号DM74ALS174MX_NL的Datasheet PDF文件第3页浏览型号DM74ALS174MX_NL的Datasheet PDF文件第4页浏览型号DM74ALS174MX_NL的Datasheet PDF文件第5页浏览型号DM74ALS174MX_NL的Datasheet PDF文件第6页浏览型号DM74ALS174MX_NL的Datasheet PDF文件第7页 
September 1986  
Revised February 2000  
DM74ALS174 • DM74ALS175  
Hex/Quad D-Type Flip-Flops with Clear  
General Description  
Features  
These positive-edge-triggered flip-flops utilize TTL circuitry  
to implement D-type flip-flop logic. Both have an asynchro-  
nous clear input, and the quad (DM74ALS175) version fea-  
tures complementary outputs from each flip-flop.  
Advanced oxide-isolated ion-implanted Schottky TTL  
process  
Pin and functional compatible with LS family counterpart  
Typical clock frequency maximum is 80 MHz  
Information at the D inputs meeting the setup time require-  
ments is transferred to the Q outputs on the positive-going  
edge of the clock pulse. Clock triggering occurs at a partic-  
ular voltage level and is not directly related to the transition  
time of the positive-going pulse. When the clock input is at  
either the HIGH or LOW level, the D input signal has no  
effect at the output.  
Switching performance guaranteed over full temperature  
and VCC supply range  
Ordering Code:  
Ordering Code Package Number  
Package Description  
DM74ALS174M  
DM74ALS174SJ  
DM74ALS174N  
DM74ALS175M  
DM74ALS175SJ  
DM74ALS175N  
M16A  
M16D  
N16E  
M16A  
M16D  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
DM74ALS174  
DM74ALS175  
© 2000 Fairchild Semiconductor Corporation  
DS006112  
www.fairchildsemi.com  

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