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DM54LS323 PDF预览

DM54LS323

更新时间: 2024-09-12 21:54:47
品牌 Logo 应用领域
美国国家半导体 - NSC 存储
页数 文件大小 规格书
8页 154K
描述
8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins

DM54LS323 数据手册

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April 1992  
DM54LS323/DM74LS323  
8-Bit Universal Shift/Storage Register  
with Synchronous Reset and Common I/O Pins  
General Description  
The ’LS323 is an 8-bit universal shift/storage register with  
Features  
Y
Common I/O for reduced pin count  
Y
TRI-STATE outputs. Its function is similar to the ’LS299  
Four operation modes: shift left, shift right, parallel load  
and store  
É
with the exception of Synchronous Reset. Parallel load in-  
puts and flip-flop outputs are multiplexed to minimize pin  
count. Separate inputs and outputs are provided for flip-  
flops Q0 and Q7 to allow easy cascading. Four operation  
modes are possible: hold (store), shift left, shift right, and  
parallel load. All modes are activated on the LOW-to-HIGH  
transition of the Clock.  
Y
Separate continuous inputs and outputs from Q0 and  
Q7 allow easy cascading  
Y
Y
Fully synchronous reset  
TRI-STATE outputs for bus oriented applications  
Connection Diagram  
Dual-In-Line Package  
TL/F/9829–1  
Order Number DM54LS323J, DM54LS323W, DM74LS323WM or DM74LS323N  
See NS Package Number J20A, M20B, N20A or W20A  
Pin Names  
Description  
CP  
Clock Pulse Input (Active Rising Edge)  
Serial Data Input for Right Shift  
Serial Data Input for Left Shift  
Mode Select Inputs  
D 0  
S
D 7  
S
S0, S1  
SR  
Synchronous Reset Input (Active LOW)  
OE1, OE2 TRI-STATE Output Enable Inputs (Active LOW)  
I/O0I/O7 Parallel Data Inputs or TRI-STATE  
Parallel Outputs  
Q0, Q7  
Serial Outputs  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9829  
RRD-B30M115/Printed in U. S. A.  

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