DM2203/2213 Multibank EDO EDRAM
512Kb x 8 Enhanced Dynamic RAM
Product Specification
Enhanced
Memory Systems Inc.
Features
■ 8Kbit SRAM Cache Memory for 12ns Random Reads Within Four
Active Pages (Multibank Cache)
■ Output Latch Enable Allows Extended Data Output (EDO) For
Faster System Operation
■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ Hidden Precharge Cycles
■ Hidden Refresh Cycles
■ Write-per-bit Option (DM2213) for Parity and Video Applications
■ Extended 64ms Refresh Period for Low Standby Power
■ Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply
■ Low Profile 300-Mil 44-Pin TSOP-II Package
■ Industrial Temperature Range Option
■ 5ns Output Enable Access Time Allows Fast Interleaving
■
256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache Fill
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
Without the Need for External Cache Control
■ A Hit Pin Outputs Status of On-chip Page Hit/Miss Comparators to
Simplify Control
Description
The Enhanced Memory Systems 4Mb EDRAM combines raw
speed with innovative architecture to offer the optimum cost-
performance solution for high performance local or main memory in
computer and embedded control systems. In most high speed
applications, zero-wait-state operation can be achieved without
secondary SRAM cache for system clock speeds of up to 83MHz
without interleaving or 132MHz with two-way interleaving. The
EDRAM outperforms conventional SRAM cache plus DRAM or
synchronous DRAM memory systems by minimizing wait states on
initial reads (hit or miss) and by eliminating writeback delays.
Architectural similarity with JEDEC DRAMs allows a single memory
controller design to support either slow JEDEC DRAMs or high speed
EDRAMs. A system designed in this manner can provide a simple
upgrade path to higher system performance.
of different organizations can be supported with the same controller
design. The 512K x 8 EDRAM implements the following additional
features which can be supported on new designs:
■ A controllable output latch provides an extended data out (EDO)
mode.
■ Cache size is increased from 2Kbits to 8Kbits. The 8Kbit cache is
organized as four 256 x 8 direct mapped row registers.
■ A hit pin is provided to tell the memory controller when a hit
occurs to one of the on-chip cache row registers.
Architecture
The EDRAM architecture has a simple integrated SRAM cache
which allows it to operate much like a page mode or static column
DRAM.
The 512K x 8 EDRAM has the same control and address interface
as Enhanced’s 4M x 1 and 1M x 4 EDRAM products so that EDRAMs
Pin Configuration
Functional Diagram
/CAL
/HIT
Column
Address
Latch
V
V
SS
1
2
3
4
5
6
7
44
43
CC
A
- A
7
0
W/R
/F
Column Decoder
V
42 /S
A
SS
DQ
41
4 - 256 X 8 Cache Pages
(Row Registers)
0
10
A
V
40
39
38
37
36
35
34
33
32
9
CC
4 - 9 Bit
Comparators
A
DQ
8
1
QLE
/G
A
DQ
7
2
Sense Amps
& Column Write Select
A
V
8
6
SS
DQ
A
5
A - A
I/O
Control
and
Data
Latches
9
3
0
10
4 - Last Row
Read Address
Latches
A
QLE
10
11
12
13
14
15
16
17
18
19
20
21
22
4
DQ - DQ
0
7
V
V
CC
SS
/G
/RE
/CAL
DQ
4
/S
Memory
Array
(2048 X 256 X 8)
Row
Address
Latch
V
V
31
30
29
28
27
26
25
24
23
SS
CC
/WE
DQ
5
A
3
DQ
6
A
2
V
A
1
CC
DQ
7
A
0
V
/WE
NC
SS
V
CC
A
- A
9
NC
NC
V
0
SS
/F
W/R
/RE
Row Adress
and
Refresh
Control
/HIT
Refresh
Counter
V
V
CC
SS
© 1996 Enhanced Memory Systems Inc. 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2105-001
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.