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DM2223T-12 PDF预览

DM2223T-12

更新时间： 2024-01-27 03:59:42
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
30页 186K
描述
Enhanced DRAM (EDRAM)

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DM2223T-12 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP, TSOP44,.36,32针数：44
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.92
Is Samacsys：N访问模式：FAST EDO/STATIC COLUMN
最长访问时间：30 ns其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH; 1K X 8 SRAM
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e0内存密度：4194304 bit
内存集成电路类型：CACHE DRAM内存宽度：8
功能数量：1端口数量：1
端子数量：44字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP
封装等效代码：TSOP44,.36,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
刷新周期：1024最大待机电流：0.001 A
子类别：DRAMs最大压摆率：0.225 mA
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：MOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

DM2223T-12 数据手册

 浏览型号DM2223T-12的Datasheet PDF文件第2页浏览型号DM2223T-12的Datasheet PDF文件第3页浏览型号DM2223T-12的Datasheet PDF文件第4页浏览型号DM2223T-12的Datasheet PDF文件第5页浏览型号DM2223T-12的Datasheet PDF文件第6页浏览型号DM2223T-12的Datasheet PDF文件第7页 
DM2223/2233 Multibank Burst EDO EDRAM  
512Kb x 8 Enhanced Dynamic RAM  
Product Specification  
Enhanced  
Memory Systems Inc.  
Features  
■ On-chip Cache Hit/Miss Comparators Automatically Maintain Cache  
Coherency Without External Cache Control  
■ Output Latch Enable Allows Extended Data Output (EDO) for  
Faster System Operation  
■ Hidden Precharge and Refresh Cycles  
■ 8Kbit SRAM Cache Memory for 12ns Random Reads Within Four  
Active Pages (Multibank Cache)  
■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page  
■ Write Posting Register for 12ns Random or Burst Writes Within  
a Page  
■ Write-per-bit Option (DM2233) for Parity and Video Applications  
■ Extended 64ms Refresh Period for Low Standby Power  
■ Low Profile 300-Mil 44-Pin TSOP-II Package  
■ Industrial Temperature Range Option  
■ 5ns Output Enable Access Time Allows Fast Interleaving  
■ Linear or Interleaved Burst Mode Configurable Without Mode  
Register Load Cycles  
■ Fast Page to Page Move or Read-Modify-Write Cycles  
Description  
The Enhanced Memory Systems 4Mb EDRAM combines raw speed  
with innovative architecture to offer the optimum cost-performance  
solution for high performance local or main memory in computer and  
embedded control systems. In most high speed applications, zero-wait-  
state operation can be achieved without secondary SRAM cache for  
system clock speeds of up to 100MHz without interleaving or 132MHz  
with two-way interleaving. The EDRAM outperforms conventional SRAM  
cache plus DRAM or synchronous DRAM memory systems by  
minimizing wait states on initial reads (hit or miss) and by eliminating  
writeback delays. Architectural similarity with JEDEC DRAMs allows a  
single memory controller design to support either slow JEDEC DRAMs  
or high speed EDRAMs. A system designed in this manner can provide  
a simple upgrade path to higher system performance.  
■ An optional synchronous burst mode for 100MHz burst transfers  
or 132MHz two-way interleaved burst transfers.  
■ A controllable output latch provides an extended data (EDO)  
mode.  
■ Cache size is increased from 2Kbits to 8Kbits. The 8Kbit cache is  
organized as four 256 x 8 direct mapped row registers. All row  
registers can be accessed without clocking /RE.  
■ Concurrent random page write and cache reads from four cache  
pages allows fast page-to-page move or read-modify-write cycles.  
Architecture  
The EDRAM architecture includes an integrated SRAM cache  
which operates much like a page mode or static column DRAM.  
The EDRAM’s SRAM cache is integrated into the DRAM array as  
tightly coupled row registers. The 512K x 8 EDRAM has a total of four  
independent DRAM memory banks each with its own 256 x 8 SRAM  
row register. Memory reads always occur from the cache row register  
The 512K x 8 EDRAM has a control and address interface  
compatible with the Enhanced 4M x 1 and 1M x 4 EDRAM products  
so that EDRAMs of different organizations can be supported with the  
same controller design. The 512K x 8 EDRAM implements the  
following additional features which can be supported on new designs: of one of these banks as specified by column address bits A and A  
8
9
Pin Configuration  
Functional Diagram  
/CAL  
BE  
BM  
0-2  
Column  
Address  
Latch  
V
V
SS  
1
2
3
4
5
6
7
44  
43  
CC  
A -A  
W/R  
0
9
/F  
and Burst  
Control  
Column Decoder  
V
42 /S  
SS  
DQ  
A
41  
0
10  
4 - 256 X 8 Cache Pages  
(Row Registers)  
V
A
9
40  
39  
38  
37  
36  
35  
34  
33  
32  
CC  
4 - 9 Bit  
DQ  
A
1
8
Comparators  
QLE  
/G  
DQ  
A
2
7
Sense Amps  
& Column Write Select  
V
A
6
8
SS  
DQ  
A
3
9
A -A  
I/O  
Control  
and  
5
0
10  
4 - Last Row  
Read Address  
Latches  
A
QLE  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
4
DQ -DQ  
0
7
V
V
CC  
SS  
Data  
Latches  
/G  
/RE  
DQ  
4
/S  
/CAL  
Memory  
Array  
(2048 X 256 X 8)  
Row  
Address  
Latch  
V
V
SS  
31  
30  
29  
28  
27  
26  
25  
24  
23  
CC  
/WE  
DQ  
5
A
3
DQ  
6
A
2
V
A
1
CC  
DQ  
7
A
0
V
SS  
/WE  
BE  
V
CC  
BM  
0
A -A  
V
0
9
SS  
/F  
W/R  
/RE  
Row Adress  
and  
Refresh  
Control  
BM  
2
BM  
1
Refresh  
Counter  
V
V
CC  
SS  
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO  
Telephone (719) 481-7000, Fax (719) 488-9095  
80921  
38-2106-001  
The information contained herein is subject to change without notice.  
Enhanced reserves the right to change or discontinue this product without notice.  
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