Datasheet > DAC1210

DAC1210

更新时间： 2024-01-04 07:17:21

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器模数转换器
页数	文件大小	规格书
18页	362K
描述
12-Bit, uP Compatible, Double-Buffered D to A Converters

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

DAC1210 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP24,.6	Reach Compliance Code：	unknown
风险等级：	5.92	转换器类型：	D/A CONVERTER
输入位码：	OFFSET BINARY, COMPLEMENTARY OFFSET BINARY	JESD-30 代码：	R-XDIP-T24
JESD-609代码：	e0	最大线性误差 (EL)：	0.05%
位数：	12	功能数量：	1
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	CERAMIC
封装代码：	DIP	封装等效代码：	DIP24,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	12/15 V	子类别：	Other Converters
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

Application Hints (Continued)

1.4 Left-Justified Data Format

1.5 16-Bit Data Bus Interface

It is important to realize that the input registers of these

DACs are arranged to accept a left-justified data word from

the microprocessor with the most significant 8 bits coming

first (Byte 1) and the lower 4 bits second. Left justification

simply means that the binary point is assumed to be located

to the left of the most significant bit. Figure 3 shows how the

12 bits of DAC data should be arranged in 2 8-bit registers

of an 8-bit processor before being written to the DAC.

The DAC1208 series provides all 12 digital input lines to

permit a direct parallel interface to a 16-bit data bus. In this

instance, double buffering is not always necessary (unless a

simultaneous updating of several DACs or a data transfer

via an external strobe is desired) so the 12-bit DAC register

can be wired to flow-through whereby its Q outputs always

reflect the state of its D inputs. The external connections

required and the timing diagram for this single buffered ap-

plication are shown in Figure 4. Note that either left or right-

justified data from the processor can be accommodated

with a 16-bit data bus.

1.6 Flow-Through Operation

Through primarily designed to provide microprocessor inter-

face compatibility, the MICRO-DACs can easily be config-

ured to allow the analog output to continuously reflect the

state of an applied digital input. This is most useful in appli-

TL/H/5690-10

don’t care

FIGURE 3. Left-Justified Data Format

Interface Timing

TL/H/5690-11

XFER and WR2 grounded; Byte 1/Byte 2 tied to V

FIGURE 4. 16-Bit Data Bus Interface for the DAC1208 Series

1...5 6 789 10 11...18

下载PDF

型号	品牌	描述	获取价格	数据表
DAC-12100	DATEL	12-Bit, 100MHz, Low-Power D/A Converters	获取价格
DAC-12100/883	DATEL	12-Bit, 100MHz, Low-Power D/A Converters	获取价格
DAC-12100/883-C	DATEL	12-Bit, 100MHz, Low-Power D/A Converters	获取价格
DAC-12100LC	DATEL	12-Bit, 100MHz, Low-Power D/A Converters	获取价格
DAC-12100LC-C	DATEL	12-Bit, 100MHz, Low-Power D/A Converters	获取价格
DAC-12100LE	DATEL	12-Bit, 100MHz, Low-Power D/A Converters	获取价格