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DAC1210 PDF预览

DAC1210

更新时间: 2024-10-27 22:50:39
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美国国家半导体 - NSC 转换器模数转换器
页数 文件大小 规格书
18页 362K
描述
12-Bit, uP Compatible, Double-Buffered D to A Converters

DAC1210 数据手册

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Application Hints (Continued)  
1.4 Left-Justified Data Format  
1.5 16-Bit Data Bus Interface  
It is important to realize that the input registers of these  
DACs are arranged to accept a left-justified data word from  
the microprocessor with the most significant 8 bits coming  
first (Byte 1) and the lower 4 bits second. Left justification  
simply means that the binary point is assumed to be located  
to the left of the most significant bit. Figure 3 shows how the  
12 bits of DAC data should be arranged in 2 8-bit registers  
of an 8-bit processor before being written to the DAC.  
The DAC1208 series provides all 12 digital input lines to  
permit a direct parallel interface to a 16-bit data bus. In this  
instance, double buffering is not always necessary (unless a  
simultaneous updating of several DACs or a data transfer  
via an external strobe is desired) so the 12-bit DAC register  
can be wired to flow-through whereby its Q outputs always  
reflect the state of its D inputs. The external connections  
required and the timing diagram for this single buffered ap-  
plication are shown in Figure 4. Note that either left or right-  
justified data from the processor can be accommodated  
with a 16-bit data bus.  
1.6 Flow-Through Operation  
Through primarily designed to provide microprocessor inter-  
face compatibility, the MICRO-DACs can easily be config-  
ured to allow the analog output to continuously reflect the  
state of an applied digital input. This is most useful in appli-  
TL/H/5690-10  
e
X
don’t care  
FIGURE 3. Left-Justified Data Format  
Interface Timing  
TL/H/5690-11  
XFER and WR2 grounded; Byte 1/Byte 2 tied to V  
.
CC  
FIGURE 4. 16-Bit Data Bus Interface for the DAC1208 Series  
8

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