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DAC1210 PDF预览

DAC1210

更新时间: 2024-02-10 04:43:02
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器模数转换器
页数 文件大小 规格书
18页 362K
描述
12-Bit, uP Compatible, Double-Buffered D to A Converters

DAC1210 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.6Reach Compliance Code:unknown
风险等级:5.92转换器类型:D/A CONVERTER
输入位码:OFFSET BINARY, COMPLEMENTARY OFFSET BINARYJESD-30 代码:R-XDIP-T24
JESD-609代码:e0最大线性误差 (EL):0.05%
位数:12功能数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP24,.6
封装形状:RECTANGULAR封装形式:IN-LINE
电源:12/15 V子类别:Other Converters
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

DAC1210 数据手册

 浏览型号DAC1210的Datasheet PDF文件第7页浏览型号DAC1210的Datasheet PDF文件第8页浏览型号DAC1210的Datasheet PDF文件第9页浏览型号DAC1210的Datasheet PDF文件第11页浏览型号DAC1210的Datasheet PDF文件第12页浏览型号DAC1210的Datasheet PDF文件第13页 
Application Hints (Continued)  
width. If this does not provide a sufficient data hold time at  
the end of the write cycle, a negative edge triggered one-  
shot can be included between the system write strobe and  
the WR pin of the DAC. This is illustrated in Figure 6 for an  
exemplary system which provides a 250 ns WR strobe time  
with a data hold time of only 10 ns.  
easily accomplished by over-compensating the DAC output  
amplifier by increasing the value of its feedback capacitor.  
In applications requiring a fast output response from the  
DAC and op amp, filtering may not be feasible. In this event,  
digital signals can be completely isolated from the DAC  
circuitry, by the use of a DM74LS374 latch, until a valid  
CS signal is applied to update the DAC. This is shown in  
Figure 7.  
The proper data set-up time prior to the latching edge (low  
to high transition) of the WR strobe, is insured if the WR  
pulse width is within spec and the data is valid on the bus for  
the duration of the DAC WR strobe.  
A single TRI-STATE data buffer such as the DM81LS95  
É
can be used to isolate any number of DACs in a system.  
Figure 8 shows this isolating circuitry and decoding hard-  
ware for a multiple DAC analog output card. Pull-up resis-  
tors are used on the buffer outputs to limit the impedance at  
the DAC digital inputs when the card is not selected. A  
unique feature of this card is that the DAC XFER strobes are  
controlled by the data bus. This allows a very flexible update  
of any combination of analog outputs via a transfer word  
which would contain a zero in the bit position assigned to  
any of the DACs required to change to a new output value.  
1.9 Digital Signal Feedthrough  
A typical microprocessor is a tremendous potential source  
of high frequency noise which can be coupled to sensitive  
analog circuitry. The fast edges of the data and address bus  
signals generate frequency components of 10’s of mega-  
hertz and may cause fast transients to appear at the DAC  
output, even when data is latched internally.  
In low frequency or DC applications, low pass filtering can  
reduce the magnitude of any fast transients. This is most  
TL/H/5690-13  
FIGURE 7. Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling  
10  

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IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,DIP,24PIN