Datasheet > DAC1210

DAC1210

更新时间： 2024-02-22 05:15:17

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器模数转换器
页数	文件大小	规格书
18页	362K
描述
12-Bit, uP Compatible, Double-Buffered D to A Converters

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DAC1210 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP24,.6	Reach Compliance Code：	unknown
风险等级：	5.92	转换器类型：	D/A CONVERTER
输入位码：	OFFSET BINARY, COMPLEMENTARY OFFSET BINARY	JESD-30 代码：	R-XDIP-T24
JESD-609代码：	e0	最大线性误差 (EL)：	0.05%
位数：	12	功能数量：	1
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	CERAMIC
封装代码：	DIP	封装等效代码：	DIP24,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	12/15 V	子类别：	Other Converters
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

Application Hints (Continued)

1.1 Automatic Transfer

The 12-bit DAC word is automatically transferred to the DAC register and the R-2R ladder when the second write (the 4 LSBs of

the data) occurs.

TL/H/5690–7

1.2 Independent Processor Transfer Control

In this case a separate address is decoded to provide the XFER signal. This allows the processor to load the next required DAC

word but not change the analog output until some time later, most useful for the simultaneous updating of several DACs in a

system where their XFER lines would be tied together.

TL/H/5690–8

1.3 Transfer via an External Strobe

This method is basically the same as the previous operation except the XFER signal is provided by a device other than the

processor. This allows the DAC to hold the code for a conditional analog output signal which will be required on demand from an

external monitoring device (an analog voltage comparator for instance).

WR2 tied to a logic low (0V)

TL/H/5690–9

1...4 5 678 9 10...18

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