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CYW2332ZI PDF预览

CYW2332ZI

更新时间： 2024-01-28 12:27:08
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管
页数 文件大小 规格书
12页 166K
描述
PLL Frequency Synthesizer, PDSO20, 0.173 INCH, TSSOP-20

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CYW2332ZI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP20,.25
针数：20Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.92
其他特性：SELECTABLE PRESCALER RATIOS OF 64/65 OR 128/129 FOR 1.2 GHZ AND 8/9 OR 16/17 FOR 600 MHZ模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：6.5 mm功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

CYW2332ZI 数据手册

 浏览型号CYW2332ZI的Datasheet PDF文件第1页浏览型号CYW2332ZI的Datasheet PDF文件第3页浏览型号CYW2332ZI的Datasheet PDF文件第4页浏览型号CYW2332ZI的Datasheet PDF文件第5页浏览型号CYW2332ZI的Datasheet PDF文件第6页浏览型号CYW2332ZI的Datasheet PDF文件第7页 
PRELIMINARY  
CYW2332  
Pin Definitions  
Pin  
No.  
(TSSO  
P)  
Pin  
No.  
(CSP)  
Pin  
No.  
Pin  
Type  
Pin Name  
(MLF)  
Pin Description  
VCC1  
1
24  
19  
P
Power Supply Connection for PLL1 and PLL2: When power  
is removed from both the VCC1 and VCC2 pins, all latched data  
is lost.  
VP1  
2
3
2
3
20  
1
P
PLL1 Charge PumpRailVoltage:Thisvoltageaccommodates  
VCO circuits with tuning voltages higher than the VCC of PLL1.  
DOPLL1  
O
PLL1 Charge Pump Output: The phase detector gain is IP/2π.  
Sense polarity can be reversed by setting the FC bit in software  
(via the Shift Register).  
FIN1  
5
6
5
6
3
4
I
I
Input to PLL1 Prescaler: Maximum frequency 1.2 GHz.  
FIN1#  
Complementary Input to PLL1 Prescaler: A bypass capacitor  
should be placed as close as possible to this pin and must be  
connected directly to the ground plane.  
OSC_IN  
FO/LD  
8
8
6
8
I
Oscillator Input: This input has a VCC/2 threshold and CMOS  
logic level sensitivity.  
10  
11  
O
Lock Detect Pin of PLL1 Section: This output is HIGH when  
the loop is locked. It is multiplexed to the output of the program-  
mable counters or reference dividers in the test program mode.  
(Refer to Table 3 for configuration.)  
CLOCK  
11  
12  
9
I
Data Clock Input: One bit of data is loaded into the Shift Reg-  
ister on the rising edge of this signal.  
DATA  
LE  
12  
13  
14  
15  
10  
11  
I
I
Serial Data Input  
Load Enable: On the rising edge of this signal, the data stored  
in the Shift Register is latched into the reference counter and  
configuration controls, PLL1 or PLL2 depending on the state of  
the control bits.  
FIN2#  
15  
17  
13  
I
Complementary Input to PLL2 Prescaler: A bypass capacitor  
should be placed as close as possible to this pin and must be  
connected directly to the ground plane.  
FIN2  
16  
18  
18  
20  
14  
16  
I
Input to PLL2 Prescaler: Maximum frequency 600 MHz.  
DOPLL2  
O
PLL2 Charge Pump Output: The phase detector gain is IP/2π.  
Sense polarity can be reversed by setting the FC bit in software  
(via the Shift Register).  
VP2  
19  
20  
22  
23  
17  
18  
P
P
PLL2 Charge PumpRailVoltage:Thisvoltageaccommodates  
VCO circuits with tuning voltages higher than the VCC of PLL2.  
VCC  
2
Power Supply Connections for PLL1 and PLL2: When power  
is removed from both the VCC1 and VCC2 pins, all latched data  
is lost.  
GND  
4, 7, 9,  
14, 17  
4,7,10,  
16, 19  
2, 5, 7,  
12, 15  
G
Analog and Digital Ground Connections: This pin must be  
grounded.  
2
1234567...12

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