CYS25G0101DX
CYS25G0101DX OC-48 SONET Transceiver (continued)
Pin Name I/O Characteristics
Signal Description
LINELOOP
LVTTL input
Line Loopback Control. When HIGH, received serial data is looped back from receive to
transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data
passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA
are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.
LOOPA
LVTTL input
Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial
data is looped back from receive input buffer to transmit output buffer, but is not routed
through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the
OUT± line driver is controlled by LINELOOP.
LOOPTIME LVTTL input
Loop Time Mode. When HIGH, the extracted receive bit-clock replaces transmit bit-clock.
When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.
Serial I/O
OUT±
Differential CML
output
DifferentialSerial DataOutput. ThisdifferentialCMLoutput(+3.3Vreferenced)iscapable
of driving terminated 50Ω transmission lines or commercial fiber-optic transmitter modules.
IN±
Differential CML
input
Differential Serial Data Input. This differential input accept the serial data stream for
deserialization and clock extraction.
Power
VCCN
VSSN
Power
Ground
Power
Ground
Power
+3.3V supply (for digital and low-speed I/O functions)
Signal and power ground (for digital and low-speed I/O functions)
+3.3V quiet power (for analog functions)
VCCQ
VSSQ
VDDQ
Quiet ground (for analog functions)
+1.5V supply for HSTL outputs[4]
the transmit FIFO has either under or overflowed. The FIFO
can be externally reset to clear the error indication or if no
action is taken, the internal clearing mechanism will clear the
FIFO in nine clock cycles. When the FIFO is being reset, the
output data is 1010.
CYS25G0101DX Operation
The CYS25G0101DX is a highly configurable device designed
to support reliable transfer of large quantities of data using
high-speed serial links. It performs necessary clock and data
recovery, clock generation, serial-to-parallel conversion, and
parallel-to-serial conversion. CYS25G0101DX also provides
various loopback functions.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a 155.52-MHz
external clock at the REFCLK input, and multiplies that clock
by 16 to generate a bit-rate clock for use by the transmit shifter.
The operating serial signaling rate and allowable range of
REFCLK frequencies is listed in Table 7. The REFCLK phase
noise limits to meet SONET compliancy are illustrated in
Figure 5. The REFCLK± input is a standard LVPECL input.
CYS25G0101DX Transmit Data Path
Operating Modes
The transmit path of the CYS25G0101DX supports 16-bit
-wide data paths.
Phase-Align Buffer
Serializer
Data from the input register is passed to a phase-align buffer
(FIFO). This buffer is used to absorb clock phase differences
between the transmit input clock and the internal character
clock.
The parallel data from the phase-align buffer is passed to the
Serializer which converts the parallel data to serial data using
the bit-rate clock generated by the Transmit PLL clock multi-
plier. TXD[15] is the most significant bit of the output word, and
is transmitted first on the serial interface.
Initialization of the phase-align buffer takes place when the
FIFO_RST input is asserted LOW. When FIFO_RST is
returned HIGH, the present input clock phase relative to
TXCLKO is set. Once set, the input clock is allowed to skew in
time up to half a character period in either direction relative to
REFCLK (i.e., ±180°). This time shift allows the delay path of
the character clock (relative to REFLCK) to change due to
operating voltage and temperature while not effecting the
desired operation. FIFO_RST is an asynchronous input.
Serial Output Driver
The serial interface Output Driver makes use of high-perfor-
mance differential Current Mode Logic (CML) to provide a
source-matched driver for the transmission lines. This driver
receives its data from the Transmit Shifters or the receive
loopback data. The outputs have signal swings equivalent to
that of standard LVPECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines.
FIFO_ERR is the transmit FIFO Error indicator. When HIGH,
Note:
4.
VDDQ equals VCC if interfacing to a parallel LVPECL interface.
Document #: 38-02009 Rev. *J
Page 5 of 15
5秒后页面跳转
NTC热敏电阻与PTC热敏电阻的应用原理及应用范围
GTO与普通晶闸管相比为什么可以自关断？为什么普通晶闸管不能呢？从GTO原理、应用范围带你了解原因及推荐型号
LF353数据手册解读：特性、应用、封装、引脚说明、电气参数及替换型号推荐
A4950资料手册解读：特性、应用、封装、引脚功能、电气参数及代换型号
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
