CYS25G0101DX
clocks these bits into the Deserializer at the bit-clock rate. The
Deserializer converts serial data into parallel data. RXD[15] is
the most significant bit of the output word and is received first
on the serial interface.
CYS25G0101DX Receive Data Path
Serial Line Receivers
A differential line receiver, IN±, is available for accepting the
input serial data stream. The serial line receiver inputs can
accommodate high wire interconnect and filtering losses or
transmission line attenuation (VSE > 25 mV, or 50 mV
peak-to-peak differential), and can be AC-coupled to +3.3V or
+5V powered fiber-optic interface modules. The common-
mode tolerance of these line receivers accommodates a wide
range of signal termination voltages.
Loopback/Timing Modes
CYS25G0101DX supports various loopback modes, as
described below.
Facility Loopback (Line Loopback with Retiming)
When the LINELOOP signal is set HIGH, the Facility Loopback
mode is activated and the high-speed serial receive data (IN±)
is presented to the high-speed transmit output (OUT±) after
retiming. In Facility Loopback mode, the high-speed receive
data (IN±) is also converted to parallel data and presented to
the low-speed receive data output pins (RXD[15:0]). The
receive recovered clock is also divided down and presented to
the low-speed clock output (RXCLK).
Lock to Data Control
Line Receiver routed to the clock and data recovery PLL is
monitored for
• status of signal detect (SD) pin
• status of LOCKREF pin.
This status is presented on the Line Fault Indicator (LFI)
output, which changes asynchronously in the cases in which
SD or LOCKREF go from HIGH to LOW. Otherwise, it changes
synchronously to the REFCLK.
Equipment Loopback (Diagnostic Loopback with Retiming)
When the DIAGLOOP signal is set HIGH, transmit data is
looped back to the RX PLL, replacing IN±. Data is looped back
from the parallel TX inputs to the parallel RX outputs. The data
is looped back at the internal serial interface and goes through
transmit shifter and the receive CDR. SD is ignored in this
mode.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of data bits from
received serial stream is performed by a Clock/Data Recovery
(CDR) block. The clock extraction function is performed by
high-performance embedded phase-locked loop (PLL) that
tracks the frequency of the incoming bit stream and aligns the
phase of the internal bit-rate clock to the transitions in the
selected serial data stream.
CDR accepts a character-rate (bit-rate * 16) reference clock
on the REFCLK input. This REFCLK input is used to ensure
that the VCO (within the CDR) is operating at the correct
frequency (rather than some harmonic of the bit-rate), to
improve PLL acquisition time, and to limit unlocked frequency
excursions of the CDR VCO when no data is present at the
serial inputs.
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the
recovered data stream is outside the limits set by the range
controls, the CDR PLL will track REFCLK instead of the data
stream. When the frequency of the selected data stream
returns to a valid frequency, the CDR PLL is allowed to track
the received data stream. The frequency of REFCLK is
required to be within ±100 ppm of the frequency of the clock
that drives the REFCLK signal of the remote transmitter to
ensure a lock to the incoming data stream.
Line Loopback Mode (Non-retimed Data)
When the LOOPA signal is set HIGH, the RX serial data is
directly buffered out to the transmit serial data. The data at the
serial output is not retimed.
Loop Timing Mode
When the LOOPTIME signal is set HIGH, the TX PLL is
bypassed and receive bit-rate clock is used for transmit side
shifter.
Reset Modes
ALL logic circuits in the device can be reset using RESET and
FIFO_RST signals. When RESET is set LOW, all logic circuits
except FIFO are internally reset. When FIFO_RST is set LOW,
the FIFO logic is reset.
Power-down Mode
CYS25G0101DX provides a global power-down signal
PWRDN. When LOW, this signal powers down the entire
device to a minimal power dissipation state. RESET and
FIFO_RST signals should be asserted LOW along with
PWRDN signal to ensure low power dissipation.
LVPECL Compliance
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When
an LFI indication is detected, external logic can toggle
selection of the input device. When such a port switch takes
place, it is necessary for the PLL to reacquire lock to the new
serial stream.
The CYS25G0101DX HSTL parallel I/O can be configured to
LVPECL compliance with slight termination modifications. On
the transmit side of the transceiver, the TXD[15:0] and TXCLKI
can be made LVPECL compliant by setting VREF (reference
voltage of a LVPECL signal) to VCC – 1.33V. To emulate an
LVPECL signal on the receiver side, VDDQ needs to be set to
3.3V and the transmission lines need to be terminated with the
Thévenin equivalent of Zο at LVPECL ref. The signal is then
attenuated using a series resistor at the driver end of the line
to reduce the 3.3V swing level to an LVPECL swing level (see
Figure 10). This circuit needs to be used on all 16 RXD[15:0]
pins, TXCLKO, and RXCLK. The voltage divider has been
calculated assuming the system is built with 50Ω transmission
lines.
External Filter
The CDR circuit uses external capacitors for the PLL filter. A
0.1-µF capacitor needs be connected between RXCN1 and
RXCP1. Similarly a 0.1-µF capacitor needs to be connected
between RXCN2 and RXCP2. The recommended packages
and dielectric material for these capacitors are 0805 X7R or
0603 X7R.
Deserializer
The CDR circuit extracts bits from the serial data stream and
Document #: 38-02009 Rev. *J
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