Datasheet > CYS25G0102DX-ATI

CYS25G0102DX-ATI

更新时间： 2024-01-25 08:21:12

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		ATM 异步传输模式电信信息通信管理电信集成电路
页数	文件大小	规格书
16页	285K
描述
ATM/SONET/SDH Transceiver, BICMOS, PQFP120,

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CYS25G0102DX-ATI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.92
JESD-30 代码：	S-PQFP-G120	JESD-609代码：	e0
端子数量：	120	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP120,.63SQ,16
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	1.5,2.5 V	认证状态：	Not Qualified
子类别：	ATM/SONET/SDH ICs	表面贴装：	YES
技术：	BICMOS	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.4 mm
端子位置：	QUAD	Base Number Matches：	1

CYS25G0102DX-ATI 数据手册

G0102DX

CYS25G0102DX

PRELIMINARY

SONET OC-48 Transceiver

Features

Functional Description

• SONET OC-48 operation

• Full Bellcore and ITU jitter compliance

• 2.488-GBaud serial signaling rate

• Multiple selectable loopback/loop-through modes

• Single 155.52-MHz reference clock

• Transmit FIFO for flexible data interface clocking

• 16-bit parallel-to-serial conversion in transmit path

• Serial to 16-bit parallel conversion in receive path

• Synchronous parallel interface

The CYS25G0102DX SONET OC-48 Transceiver is a commu-

nications building block for high-speed SONET data commu-

nications.It provides complete parallel-to-serial and serial-to-

parallel conversion, clock generation, and clock and data

recovery operations in a single chip, optimized for full SONET

compliance.

Transmit Path

New data is accepted at the 16-bit parallel transmit interface

at rate of 155.52 Mbits/second. This data is passed to a small

integrated FIFO to allow flexible transfer of data between the

SONET processor and the transmit serializer. As each 16-bit

word is read from the transmit FIFO, it is serialized and sent

out the high-speed differential line driver at a rate of 2.488

Gbits/second.

— LVPECL-compliant

— HSTL-compliant

• Internal transmit and receive PLLs

• Differential CML serial input

— 50 mV input sensitivity

Receive Path

As serial data is received at the differential line receiver, it is

passed to a clock and data recovery (CDR) phase-locked loop

(PLL), which extracts a precision low-jitter clock from the

transitions in the data stream. This bit-rate clock is then used

to sample the data stream and receive the data. Every 16 bit-

times, a new word is presented at the receive parallel interface

along with a 155.52-MHz synchronous clock.

— Internal termination and DC-restoration

• Differential CML serial output

— Source matched for 50Ω transmission lines

• Direct interface to standard fiber-optic modules

• 0.550 watt typical power

• 120-pin 14-mm × 14-mm TQFP

• Standby power-saving mode for inactive loops

• 0.25µ SiGe BiCMOS technology

Parallel Interface

The parallel I/O interface supports high-speed bus communi-

cations using HSTL signaling levels to minimize both power

consumption and board landscape. The HSTL outputs are

capable of driving unterminated transmission lines of less than

70 mm, and terminated 50Ω transmission lines of more than

twice that length.

• Control inputs are 3.3V tolerant

The CYS25G0102DX transceiver’s parallel HSTL I/O can also

be configured to operate at LVPECL signaling levels. This can

be done externally by changing V_DDQ, V_REF, and creating a

simple circuit at the termination of the transceiver’s parallel

output interface and proper biasing of the parallel input

interface.

SONET Data

Processor

CYS25G0102DX

TXD[15:0]

TXCLKI

Transmit Data

Interface

FIFO_RST

FIFO_ERR

TXCLKO

155.52 MHz

BITS Time

Reference

REFCLK±

Host Bus

Interface

RXD[15:0]

RXCLK

Receive Data

Interface

IN+

IN–

OUT–

OUT+

RD+

RD–

TD–

TD+

Serial Data

LOOPTIME

DIAGLOOP

LOOPA

Data & Clock

Direction

Control

Optical

XCVR

Optical

Fiber Links

LINELOOP

RESET

PWRDN

LOCKREF

LFI

Status and

System

Control

Figure 1. CYS25G0102DX System Connections

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-02026 Rev. *A

Revised January 30, 2002

12 3 4 5 6 7...16

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