CYS25G0101DX
SONET OC-48 Transceiver
SONET OC-48 Transceiver
Features
Functional Description
■ SONET OC-48 operation
The CYS25G0101DX SONET OC-48 Transceiver is
communications building block for high speed SONET data
communications. It provides complete parallel-to-serial and
serial-to-parallel conversion, clock generation, and clock and
data recovery operations in a single chip optimized for full
SONET compliance.
a
■ Bellcore and ITU jitter compliance
■ 2.488 GBaud serial signaling rate
■ Multiple selectable loopback or loop through modes
■ Single 155.52 MHz reference clock
Transmit Path
■ Transmit FIFO for flexible data interface clocking
■ 16-bit parallel-to-serial conversion in transmit path
■ Serial-to-16-bit parallel conversion in receive path
New data is accepted at the 16-bit parallel transmit interface at
a rate of 155.52 MHz. This data is passed to a small integrated
FIFO to enable flexible transfer of data between the SONET
processor and the transmit serializer. As each 16-bit word is read
from the transmit FIFO, it is serialized and sent out to the high
speed differential line driver at a rate of 2.488 Gbits per second.
■ Synchronous parallel interface
❐ LVPECL compliant
❐ HSTL compliant
Receive Path
■ Internal transmit and receive phase-locked loops (PLLs)
As serial data is received at the differential line receiver, it is
passed to a clock and data recovery (CDR) PLL that extracts a
precision low jitter clock from the transitions in the data stream.
This bit rate clock is used to sample the data stream and receive
the data. Every 16-bit times, a new word is presented at the
receive parallel interface along with a clock.
■ Differential CML serial input
❐ 50 mV input sensitivity
❐ 100internal termination and DC restoration
■ Differential CML serial output
❐ Sourcematchedfor50 transmissionlines(100 differential
transmission lines)
Parallel Interface
The parallel I/O interface supports high speed bus communica-
tions using HSTL signaling levels to minimize both power
consumption and board landscape. The HSTL outputs are
capable of driving unterminated transmission lines of less than
70 mm and terminated 50 transmission lines of more than twice
that length.
■ Direct interface to standard fiber optic modules
■ Less than 1.0W typical power
■ 120-pin 14 mm × 14 mm TQFP
■ Standby power saving mode for inactive loops
■ 0.25 BiCMOS technology
The CYS25G0101DX Transceiver’s parallel HSTL I/O can also
be configured to operate at LVPECL signaling levels. This is
done externally by changing VDDQ, VREF and creating a simple
circuit at the termination of the transceiver’s parallel output
interface.
■ Pb-free packages available
Cypress Semiconductor Corporation
Document Number: 38-02009 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 24, 2013