Datasheet > CYS25G0101DX-AEXC

CYS25G0101DX-AEXC

更新时间： 2024-02-26 16:00:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		ATM 异步传输模式电信信息通信管理电信集成电路
页数	文件大小	规格书
22页	384K
描述
Transceiver, 1-Func, BICMOS, PQFP120, 14 X 14 MM, 1 MM HEIGHT, LEAD FREE, MS-026, TQFP-120

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CYS25G0101DX-AEXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	HTFQFP, TQFP120,.64SQ,16
针数：	120	Reach Compliance Code：	compliant
ECCN代码：	5A991.B.1	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	5.77
应用程序：	SONET	JESD-30 代码：	S-PQFP-G120
JESD-609代码：	e3	长度：	14 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	120	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	HTFQFP	封装等效代码：	TQFP120,.64SQ,16
封装形状：	SQUARE	封装形式：	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	1.5,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	ATM/SONET/SDH ICs	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BICMOS
电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.4 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

CYS25G0101DX-AEXC 数据手册

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CYS25G0101DX

Pin Descriptions (continued)

CYS25G0101DX OC-48 SONET Transceiver

Pin Name

I/O Characteristics

Signal Description

Loop Control Signals

DIAGLOOP LVTTL input

Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive

clock and data recovery. It is then presented at the RXD[15:0] outputs. When LOW, received

serial data is routed through the receive clock and data recovery. It is then presented at the

RXD[15:0] outputs.

LINELOOP

LOOPA

LVTTL input

Line Loopback Control. When HIGH, received serial data is looped back from receive to

transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data

passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA

are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.

Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial

data is looped back from receive input buffer to transmit output buffer but is not routed

through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the

OUT± line driver is controlled by LINELOOP.

LOOPTIME

Loop Time Mode. When HIGH, the extracted receive bit clock replaces transmit bit clock.

When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.

Serial I/O

OUT±

Differential CML

output

Differential Serial Data Output. This differential CML output (+3.3 V referenced) is capable

of driving terminated 50 transmission lines or commercial fiber optic transmitter modules.

IN±

Differential CML

input

Differential Serial Data Input. This differential input accepts the serial data stream for

deserialization and clock extraction.

Power

V_CCN

V_SSN

Power

Ground

Power

Ground

Power

+3.3 V supply (for digital and low speed IO functions)

Signal and power ground (for digital and low speed IO functions)

+3.3 V quiet power (for analog functions)

V_CCQ

V_SSQ

V_DDQ

Quiet ground (for analog functions)

+1.5 V supply for HSTL outputs^[4]

Note

equals V if interfacing to a parallel LVPECL interface.

DDQ CC

Document Number: 38-02009 Rev. *O

Page 7 of 22

1...4 5 678 9 10...22

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