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CYIWOSC3000AA

更新时间： 2024-02-07 15:11:32
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 传感器
页数 文件大小 规格书
37页 2100K
描述
3.1 Megapixel CMOS Sensor

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CYIWOSC3000AA 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
风险等级：5.76其他特性：ELECTRONIC ROLLING SHUTTER
阵列类型：FULL FRAME主体宽度：14.22 mm
主体高度：2.1 mm主体长度或直径：14.22 mm
数据速率：48 Mbps动态范围：55 dB
帧速率：14 fps水平像素：2048
外壳：PLASTIC主时钟：48 MHz
安装特点：SURFACE MOUNT最高工作温度：70 °C
最低工作温度：-30 °C光学格式：1/2.80 inch
输出接口类型：I2C INTERFACE输出范围：0.20-1.90V
输出类型：DIGITAL VOLTAGE封装形状/形式：SQUARE
像素大小：2.54X2.54 µm传感器/换能器类型：IMAGE SENSOR,CMOS
最大供电电压：3.1 V最小供电电压：2.5 V
表面贴装：YES端接类型：SOLDER
垂直像素：1536Base Number Matches：1

CYIWOSC3000AA 数据手册

 浏览型号CYIWOSC3000AA的Datasheet PDF文件第7页浏览型号CYIWOSC3000AA的Datasheet PDF文件第8页浏览型号CYIWOSC3000AA的Datasheet PDF文件第9页浏览型号CYIWOSC3000AA的Datasheet PDF文件第11页浏览型号CYIWOSC3000AA的Datasheet PDF文件第12页浏览型号CYIWOSC3000AA的Datasheet PDF文件第13页 
CYIWOSC3000AA  
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11  
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13 14  
15  
16  
0
HSYNC  
DATVAL  
2047  
…
0
1
2
3
…
2043 2045 2046 2047  
…
PIXDATA  
MOD=00  
MOD=01  
MOD=10  
MOD=11  
Figure 6-2. Row Timing  
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8
9
10  
11  
12  
13 14  
15  
16 17  
0
18  
19  
HSYNC  
DATVAL  
2047  
…
0
1
2
3
4
5
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…
2043 2045 2046 2047  
…
PIXDATA  
MOD=00  
MOD=01  
MOD=10  
MOD=11  
Figure 6-3. Row Timing With Binning  
PIXCLK mode = 11 is typically only used in DATVAL mode.  
Otherwise, the processor has to clock in every pixel in a frame  
and then compute which ones are valid and which ones re not  
based on the bin/subsampling modes.  
Where Total number of Rows per frame =RowNum(register  
0x4 and 0x5 +1)+ VBLANK(0xC and 0xD) + Number of Dark  
rows.  
The RowNum register will have a value 1 less than actual  
number of active rows and hence an addition of 1 in the  
formula.  
6.2  
Frames per Second and Integration Time  
Calculation  
The Dark rows are the optically black rows located towards the  
periphery to calculate the black level. At least 4 rows must be  
turned on to properly compute the dark current. By default, the  
middle 4 rows are turned on which typically are the best for  
computing Dark current. Please refer section 7.2.36.  
The number of frames per second taken by the Osprey is  
programmable. It can vary from less then 1 fps to 14 fps in full  
resolution capture mode (and can be much higher in reduced  
resolution modes). The frame rate is dictated by input clk  
frequency, the total number of rows output per frame and the  
time required to read out a single row. The total number of rows  
output and the time required to output a row can be calculated  
using simple formula’s based on I2c register reads.  
Integration Time Calculation  
TINT (in Seconds) = COLCNT (register 0xa8 and 0xa9) *  
INTTIME (register 0xE and 0xF) / Clock Frequency  
It is recommended that INTTIME should not be set larger than  
the Total Number of Rows per Frame.  
RowNum register (0x4) stores the number of active rows  
output.COLCNT register (0xa8) stores the # of clks required to  
read out a single row (hence time required to read out a single  
row is COLCNT / CLK FREQ. COLCNT is modified based on  
active number of columns output (COLNUM register (0x6) and  
the HBLANK register (0x8,0x9), which adds additional clk  
cycles onto the end of the row readout). Note that COLCNT is  
a 12bit register.  
6.3  
Output Data Timing  
The Pixel Output bus has programmable polarities for the  
clock and the sync signals to simplify timing to the back-end  
processor. The timing of all of the signals is relative to PIXCLK.  
The delay time for HSYNC, VSYNC and the PIXDAT bus to be  
valid relative to the selected edge of PIXCLK is a minimum of  
0 ns (Ddsmin) and a maximum of 4 ns (Tdsmax).  
Frames/Second = Clock Frequency / (Total number of Rows  
per frame * COLCNT (register 0xa8 and 0xa9))  
Document #: 38-19009 Rev. *E  
Page 10 of 37  
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