Datasheet > CYK001M16ZCCA

CYK001M16ZCCA

更新时间： 2022-11-25 13:02:37

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	312K
描述
16-Mbit (1M x 16) Pseudo Static RAM

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CYK001M16ZCCA 数据手册

CYK001M16ZCCA

MoBL3™

16-Mbit (1M x 16) Pseudo Static RAM

(I/O₀through I/O₁₅) are placed in a high-impedance state

when: deselected (CE HIGH), outputs are disabled (OE

HIGH), both Byte High Enable and Byte Low Enable are

disabled (BHE, BLE HIGH), or during a write operation (CE

LOW and WE LOW).

Writing to the device is accomplished by asserting Chip

Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low

Enable (BLE) is LOW, then data from I/O pins (I/O₀through

I/O₇), is written into the location specified on the address pins

(A₀through A₁₇). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₇).

Features

• Wide voltage range: 2.70V–3.30V

• Access Time: 55 ns, 70 ns

• Ultra-low active power

— Typical active current: 3 mA @ f = 1 MHz

— Typical active current: 13 mA @ f = f_max

• Ultra low standby power

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Deep Sleep Mode

Reading from the device is accomplished by asserting Chip

Enable (CE)and Output Enable (OE) inputs LOW while forcing

the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is

LOW, then data from the memory location specified by the

address pins will appear on I/O₀to I/O₇. If Byte High Enable

(BHE) is LOW, then data from memory will appear on I/O₈to

• Offered in a 48-ball BGA Package

Functional Description

The CYK001M16ZCCAU is a high-performance CMOS

Pseudo static RAM organized as 1M words by 16 bits that

supports an asynchronous memory interface. This device

features advanced circuit design to provide ultra-low active

current. This is ideal for providing More Battery Life™ (MoBL^®)

in portable applications such as cellular telephones. The

device can be put into standby mode when deselected (CE

HIGH or both BHE and BLE are HIGH). The input/output pins

I/O₁₅. Refer to the truth table for a complete description of read

and write modes.

This device incorporates a Low Power mode wherein data

integrity is not guaranteed, but Power Consumption reduces

to less than 100 µW. This mode (Deep Sleep Mode) is enabled

by driving ZZ LOW.See the Truth Table for a complete

description of Read, Write, and Deep Sleep mode.

DATA IN DRIVERS

Logic Block Diagram

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

1M × 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

BLE

Power-Down

Circuit

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05454 Rev. *B

Revised May 15, 2004

12 3 4 5 6 7...11

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与CYK001M16ZCCA相关器件

型号	品牌	描述	获取价格	数据表
CYK001M16ZCCAU	ETC	Memory	获取价格
CYK001M16ZCCAU-55BAI	CYPRESS	16-Mbit (1M x 16) Pseudo Static RAM	获取价格
CYK001M16ZCCAU-55BAXI	CYPRESS	Pseudo Static RAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, FBGA-48	获取价格
CYK001M16ZCCAU-70BAI	CYPRESS	16-Mbit (1M x 16) Pseudo Static RAM	获取价格
CYK001M16ZCCAU-70BAXI	CYPRESS	Pseudo Static RAM, 1MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, FBGA-48	获取价格
CYK001M16ZCCAU-FVI55	CYPRESS	Pseudo Static RAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48	获取价格

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