Datasheet > 暂无类别数据> CYK128K16MCCBU-70BVIT

CYK128K16MCCBU-70BVIT

更新时间： 2024-01-29 00:54:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器
页数	文件大小	规格书
9页	179K
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CYK128K16MCCB

2-Mbit (128K x 16) Pseudo Static RAM

can be put into standby mode when deselected (CE HIGH or

both BHE and BLE are HIGH). The input/output pins (I/O₀

through I/O₁₅) are placed in a high-impedance state when the

chip is deselected (CE HIGH), or when the outputs are

disabled (OE HIGH), or when both Byte High Enable and Byte

Low Enable are disabled (BHE, BLE HIGH), or during a write

operation (CE LOW and WE LOW).

Features

• Wide voltage range: 2.70V–3.30V

• Access Time: 55 ns, 70 ns

• Ultra-low active power

— Typical active current: 1mA @ f = 1 MHz

— Typical active current: 14 mA @ f = f_max(For 55-ns)

— Typical active current: 8 mA @ f = f_max(For 70-ns)

• Ultra low standby power

Writing to the device is accomplished by asserting Chip

Enable (CE LOW) and Write Enable (WE) input LOW. If Byte

Low Enable (BLE) is LOW, then data from I/O pins (I/O₀

through I/O₇), is written into the location specified on the

address pins (A₀through A₁₇). If Byte High Enable (BHE) is

LOW, then data from I/O pins (I/O₈through I/O₁₅) is written

into the location specified on the address pins (A₀through

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Offered in a 48-ball BGA Package

A₁₆).

Reading from the device is accomplished by asserting Chip

Enable (CE LOW) and Output Enable (OE) LOW while forcing

the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is

LOW, then data from the memory location specified by the

address pins will appear on I/O₀to I/O₇. If Byte High Enable

(BHE) is LOW, then data from memory will appear on I/O₈to

I/O₁₅. Refer to the truth table for a complete description of read

and write modes.

Functional Description^[1]

The CYK128K16MCCB is a high-performance CMOS Pseudo

Static RAM organized as 128K words by 16 bits that supports

an asynchronous memory interface. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

128K × 16

RAM Array

I/O0 – I/O7

I/O8 – I/O15

A ₂

A ₁

A ₀

COLUMN DECODER

BHE

BLE

Power-Down

Circuit

BHE

BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05584 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised January 27, 2005

12 3 4 5 6 7...9

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