Datasheet > CYK001M16ZCCA

CYK001M16ZCCA

更新时间： 2022-11-25 13:02:37

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	312K
描述
16-Mbit (1M x 16) Pseudo Static RAM

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数据手册

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CYK001M16ZCCA 数据手册

CYK001M16ZCCA

MoBL3™

Switching Characteristics Over the Operating Range^{[10, 11, 12, 13, 14]}

55 ns^[14]

Max.

70 ns

Parameter

Read Cycle

t_RC

Description

Min.

55^[14]

Min.

Max.

Unit

Read Cycle Time

Address to Data Valid

Data Hold from Address Change

CE LOW to Data Valid

OE LOW to Data Valid

OE LOW to LOW Z^{[11, 13]}

OE HIGH to High Z^{[11, 13]}

CE LOW to Low Z^{[11, 13]}

CE HIGH to High Z^{[11, 13]}

BLE/BHE LOW to Data Valid

BLE/BHE LOW to Low Z^{[11, 13]}

BLE/BHE HIGH to HIGH Z^{[11, 13]}

Address Skew

t_AA

t_OHA

t_ACE

t_DOE

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_DBE

t_LZBE

t_HZBE

[14]

t_SK

Write Cycle^[12]

t_WC

t_SCE

t_AW

t_HA

Write Cycle Time

CE LOW to Write End

Address Set-up to Write End

Address Hold from Write End

Address Set-up to Write Start

WE Pulse Width

BLE/BHE LOW to Write End

Data Set-up to Write End

Data Hold from Write End

WE LOW to High-Z^{[11, 13]}

WE HIGH to Low-Z^{[11, 13]}

t_SA

t_PWE

t_BW

t_SD

t_HD

t_HZWE

t_LZWE

Notes:

10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V

/2, input pulse levels

CC(typ)

of 0V to V

, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.

OL OH

CC(typ.)

11. t

, t

, and t

transitions are measured when the outputs enter a high impedence state.

HZOE HZCE HZBE

HZWE

12. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any

of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates

the write.

13. High-Z and Low-Z parameters are characterized and are not 100% tested.

14. To achieve 55-ns performance, the read access should be CE controlled. In this case t

is the critical parameter and t is satisfied when the addresses are

ACE

stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle

Document #: 38-05454 Rev. *B

Page 5 of 11

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